• Supports 66-MHz microprocessor cache systems with
zero wait states
• 64K by 32 common I/O
• Low Standby Power (1.65 mW, L version)
• Fast clock-to-output times
— 7.5 ns (117-MHz version)
• Two-bit wraparound counter supporting either inter-
leaved or linear burst sequence
• Separate processor and controller address strobes
provide direct interface with the processor and external
cache controller
• Synchronous self-timed write
• Asynchronous Output Enable
• 3.3V I/Os
• JEDEC-standard pinout
• 100-pin TQFP packaging
• ZZ “sleep” mode
Functional Description
The CY7C1336 is a 3.3V 64K by 32 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
7.5 ns (117-MHz version). A 2-bit On-Chip Counter captures
the first address in a burst and increments the address auto-
matically for the rest of the burst access.
The CY7C1336 allows both interleaved or linear burst se-
quences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the processor
address strobe (ADSP) or the cache controller address strobe
(ADSC) inputs. Address advancement is controlled by the ad-
dress advancement (ADV) input.
A synchronous self-timed write mechanism is provided to sim-
plify the write interface. A synchronous Chip Enable input and
an asynchronous Output Enable input provide easy control for
bank selection and output three-state control.
Logic Block Diagram
CLK
ADV
ADSC
ADSP
A
[15:0]
GW
BWE
BW
3
BW
2
MODE
(A
0
,A
1
) 2
BURST Q
0
CE COUNTER
Q
1
CLR
Q
ADDRESS
CE REGISTER
D
D
DQ[31:24] Q
BYTEWRITE
REGISTERS
14
16
16
14
64KX32
MEMORY
ARRAY
D DQ[23:16] Q
BYTEWRITE
REGISTERS
D
Q
DQ[15:8]
BYTEWRITE
REGISTERS
Q
DQ[7:0]
BYTEWRITE
REGISTERS
BW
1
D
BW
0
CE
1
CE
2
CE
3
32
32
D
ENABLE Q
CE REGISTER
CLK
INPUT
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQ
[31:0]
Selection Guide
7C1336–117
7C1336L-117
7.5
300
270
5.0
7C1336–100
7C1336L-100
8.0
260
235
5.0
7C1336–66
7C1336L-66
9.0
260
235
5.0
Maximum Access Time (ns)
Maximum Operating Current
(mA)
L
Maximum Standby Current (mA)
Pentium is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
March 3, 1999
PRELIMINARY
Pin Configuration
CY7C1336
100-Lead TQFP
OE
ADSC
BW
1
BW
0
CE
1
CE
2
CE
3
V
DD
V
SS
ADSP
ADV
84
83
BWE
BW
3
BW
2
CLK
GW
A6
A7
A
8
82
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
NC
DQ
16
DQ
17
V
DDQ
V
SSQ
DQ
18
DQ
19
BYTE2
DQ
20
DQ
21
V
SSQ
V
DDQ
DQ
22
DQ
23
V
SSQ
V
DD
NC
V
SS
DQ
24
DQ
25
V
DDQ
V
SSQ
DQ
26
DQ
27
DQ
28
DQ
29
V
SSQ
V
DDQ
DQ
30
DQ
31
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
CY7C1336
pinout
100
81
A
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
NC
DQ
15
DQ
14
V
DDQ
V
SSQ
DQ
13
DQ
12
DQ
11
DQ
10
V
SSQ
V
DDQ
DQ
9
DQ
8
V
SS
NC
V
DD
ZZ
DQ
7
DQ
6
V
DDQ
V
SSQ
DQ
5
DQ
4
DQ
3
DQ
2
V
SSQ
V
DDQ
DQ
1
DQ
0
NC
BYTE1
BYTE3
BYTE0
MODE
A
5
A
4
A
3
A
2
A
1
A
0
A
14
A
15
DNU
DNU
A
10
A
11
A
12
DNU
DNU
V
SS
2
V
DD
A
13
NC
PRELIMINARY
Functional Description
(continued)
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are sat-
isfied at clock rise: (1) CE
1
, CE
2
, and CE
3
are all asserted
active, and (2) ADSP is asserted LOW. The addresses pre-
sented are loaded into the address register and the burst
counter/control logic and delivered to the RAM core. The write
inputs (GW, BWE, and BW
[3:0]
) are ignored during this first
clock cycle. If the write inputs are asserted active (see Write
Cycle Description Table for appropriate states that indicate a
write) on the next clock rise, the appropriate data will be
latched and written into the device. Byte writes are allowed.
During byte writes, BW
0
controls DQ
[7:0]
, BW
1
controls
DQ
[15:8]
, BW
2
controls DQ
[23:16]
, and BW
3
controls DQ
[31:24]
.
All I/Os are three-stated during a byte write. Since this is a
common I/O device the asynchronous OE input signal must be
deasserted and the I/Os must be three-stated prior to the pre-
sentation of data to DQ
[31:0]
. As a safety precaution, the data
lines are three-stated once a write cycle is detected, regard-
less of the state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE
1
, CE
2
, and CE
3
are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BW
[3:0]
)
indicate a write access. ADSC is ignored if ADSP is active LOW.
The addresses presented are loaded into the Address Regis-
ter, burst counter/control logic and delivered to the RAM core.
The information presented to DQ
[31:0]
will be written into the
specified address location. Byte writes are allowed. During
byte writes, BW
0
controls DQ
[7:0]
, BW
1
controls DQ
[15:8]
, BW
2
controls DQ
[23:16]
, and BW
3
controls DQ
[31:24]
. All I/Os are
three-stated when a write is detected, even a byte write. Since
this is a common I/O device, the asynchronous OE input signal
must be deasserted and the I/Os must be three-stated prior to
the presentation of data to DQ
[31:0]
. As a safety precaution, the
data lines are three-stated once a write cycle is detected, re-
gardless of the state of OE.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE
1
, CE
2
, and CE
3
are all as-
serted active, and (2) ADSP or ADSC is asserted LOW (if the
access is initiated by ADSC, the write inputs must be deassert-
ed during this first cycle). The address presented to the ad-
dress inputs is latched into the Address Register, burst counter
/control logic and presented to the memory core. If the OE
input is asserted LOW, the requested data will be available at
CY7C1336
the data outputs a maximum to t
CDV
after clock rise. ADSP is
ignored if CE
1
is HIGH.
Burst Sequences
The CY7C1336 provides an on-chip 2-bit wraparound burst
counter inside the SRAM. The burst counter is fed by A
[1:0]
,
and can follow either a linear or interleaved burst order. The
burst order is determined by the state of the MODE input. A
LOW on MODE will select a linear burst sequence. A HIGH on
MODE will select an interleaved burst order. Leaving MODE
unconnected will cause the device to default to an interleaved
burst sequence.
Table 1. Counter Implementation for the Intel
Pentium®/80486 Processor’s Sequence
First
Address
A
[1:0]
00
01
10
11
Second
Address
A
[1:0]
01
00
11
10
Third
Address
A
[1:0]
10
11
00
01
Fourth
Address
A
[1:0]
11
10
01
00
Table 2. Counter Implementation for a Linear Sequence
First
Address
A
[1:0]
00
01
10
11
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ HIGH
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed. Ac-
cesses pending when entering the “sleep” mode are not con-
sidered valid nor is the completion of the operation guaran-
teed. The device must be deselected prior to entering the
“sleep” mode. CE
1
, CE
2
, CE
3
, ADSP, and ADSC must remain
inactive for the duration of t
ZZREC
after the ZZ input returns
LOW. Leaving ZZ unconnected defaults the device into an ac-
tive state.
Second
Address
A
[1:0]
01
10
11
00
Third
Address
A
[1:0]
10
11
00
01
Fourth
Address
A
[1:0]
11
00
01
10
3
PRELIMINARY
Cycle Description Table
[1, 2, 3]
Cycle Description
Deselected Cycle,
Power-Down
Deselected Cycle,
Power-Down
Deselected Cycle,
Power-Down
Deselected Cycle,
Power-Down
Deselected Cycle,
Power-Down
SNOOZE MODE,
Power-Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
ADD
Used
None
None
None
None
None
None
External
External
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
CE
1
H
L
L
L
X
X
L
L
L
L
L
X
X
H
H
X
H
X
X
H
H
X
H
CE
3
X
X
H
X
X
X
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
CE
2
X
L
X
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
ZZ
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
ADSP
X
L
L
H
H
X
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
ADSP
L
X
X
L
L
X
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
ADV
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
WE
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
L
H
H
H
H
L
L
CY7C1336
OE
X
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
CLK
L-H
L-H
L-H
L-H
L-H
X
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
HIGH-Z
Q
High-Z
D
Q
High-Z
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
D
D
Notes:
1. X=Don't Care, 1=Logic HIGH, 0=Logic LOW.
2. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
[3:0].
Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE
is a don't care for the remainder of the write cycle.
3. OE is asynchronous and is not sampled with the clock rise. During a read cycle DQ=High-Z when OE is inactive, and DQ=data when OE is active.
4
PRELIMINARY
Pin Descriptions
TQFP Pin
Number
85
Name
ADSC
I/O
Input-
Synchronous
Input-
Synchronous
Description
CY7C1336
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted
LOW, A
[15:0]
is captured in the address registers. A
[1:0]
are also loaded into the burst
counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted
LOW, A
[15:0]
is captured in the address registers. A
[1:0]
are also loaded into the burst
counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP
is ignored when CE
1
is deasserted HIGH.
A
1
, A
0
Address Inputs, These inputs feed the on-chip burst counter as the LSBs as
well as being used to access a particular memory location in the memory array.
Address Inputs used in conjunction with A
[1:0]
to select one of the 64K address loca-
tions. Sampled at the rising edge of the CLK, if CE
1
, CE
2
, and CE
3
are sampled active,
and ADSP or ADSC is active LOW.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes.
Sampled on the rising edge. BW
0
controls DQ
[7:0]
, BW
1
controls DQ
[15:8]
, BW
2
con-
trols DQ
[23:16]
, BW
3
controls DQ
[31:24]
. See Write Cycle Description Table for further
details.
Advance Input used to advance the on-chip address counter. When LOW the internal
burst counter is advanced in a burst sequence. The burst sequence is selected using
the MODE input.
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
Global Write Input, active LOW. Sampled on the rising edge of CLK. This signal is
used to conduct a global write, independent of the state of BWE and BW
[3:0]
. Global
writes override byte writes.
Clock Input. Used to capture all synchronous inputs to the device.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in con-
junction with CE
2
and CE
3
, to select/deselect the device. CE
1
gates ADSP.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in con-
junction with CE
1
and CE
3
to select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in con-
junction with CE
1
and CE
2
to select/deselect the device.
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are
three-stated, and act as input data pins.
Snooze Input. Active HIGH asynchronous. When HIGH, the device enters a low power
standby mode in which all other inputs are ignored, but the data in the memory array
is maintained. Leaving ZZ floating or NC will default the device into an active state.
Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved
burst order. Pulled LOW selects the linear burst order. When left floating or NC, de-
faults to interleaved burst order.
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by A
[15:0]
during the previous clock rise of the read cycle.
The direction of the pins is controlled by OE in conjunction with the internal control
logic. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ
[31:0]
are placed in a three-state condition. The outputs are automatically three-stated when
a WRITE cycle is detected.
84
ADSP
36, 37
49
−44,
81–82,
99–100,
32–35
96–93
A
[1:0]
A
[15:2]
Input-
Synchronous
Input-
Synchronous
BW
[3:0]
Input-
Synchronous
83
ADV
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
Input-
Asynchronous
-
87
88
BWE
GW
89
98
97
92
86
CLK
CE
1
CE
2
CE
3
OE
64
ZZ
31
MODE
29–28,
25–22,
19–18,
13–12,
9–6, 3–2,
79–78,
75–72,
69–68,
63–62,
59–56,
53–52
15, 41, 65,
91
DQ
[31:0]
I/O-
Synchronous
V
DD
Power Supply
Power supply inputs to the core of the device. Should be connected to 3.3V power
