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CY7C1355B
CY7C1357B
9-Mbit (256K x 36/512K x 18) Flow-Through
SRAM with NoBL™ Architecture
Features
• No Bus Latency™ (NoBL™) architecture eliminates
dead cycles between write and read cycles.
• Can support up to 133-MHz bus operations with zero
wait states
— Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
• 3.3V/2.5V I/O power supply
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
— 7.0 ns (for 117-MHz device)
— 7.5 ns (for 100-MHz device)
• Clock Enable (CEN) pin to enable clock and suspend
operation
• Synchronous self-timed writes
• Asynchronous Output Enable
• Offered in JEDEC-standard 100 TQFP, 119-Ball BGA and
165-Ball fBGA packages
• Three chip enables for simple depth expansion.
• Automatic Power-down feature available using ZZ
mode or CE deselect.
• JTAG boundary scan for BGA and fBGA packages
• Burst Capability—linear or interleaved burst order
• Low standby power
Functional Description
[1]
The CY7C1355B/CY7C1357B is a 3.3V, 256K x 36/ 512K x 18
Synchronous Flow-through Burst SRAM designed specifically
to support unlimited true back-to-back Read/Write operations
without
the
insertion
of
wait
states.
The
CY7C1355B/CY7C1357B is equipped with the advanced No
Bus Latency (NoBL) logic required to enable consecutive
Read/Write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput
of data through the SRAM, especially in systems that require
frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the two or four Byte Write
Select (BW
X
) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Selection Guide
133 MHz
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
6.5
250
30
117 MHz
7.0
220
30
100 MHz
7.5
180
30
Unit
ns
mA
mA
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05117 Rev. *C
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised June 29, 2004
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CY7C1355B
CY7C1357B
1
Logic Block Diagram – CY7C1355B (256K x 36)
A0, A1, A
MODE
CLK
CEN
C
CE
ADV/LD
C
WRITE ADDRESS
REGISTER
ADDRESS
REGISTER
A1
D1
A0
D0
Q1 A1'
A0'
Q0
BURST
LOGIC
ADV/LD
BW
A
BW
B
BW
C
A0, A1, A
BW
D
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
ADDRESS
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
E
REGISTER
CE
MODE
WE
CLK
CEN
C
ADV/LD
C
A1
D1
A0
D0
BURST
LOGIC
Q1 A1'
A0'
Q0
DQs
DQP
A
DQP
B
DQP
C
DQP
D
OE
CE1
CE2
CE3
ZZ
READ LOGIC
WRITE ADDRESS
REGISTER
INPUT
E
REGISTER
SLEEP
CONTROL
ADV/LD
BW
A
2
Logic Block Diagram –
A0, A1, A
BW
B
WRITE REGISTRY
AND DATA COHERENCY
CY7C1357B (512K x 18)
CONTROL LOGIC
ADDRESS
REGISTER
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
E
DQs
DQP
A
DQP
B
WE
CE
MODE
CLK
CEN
C
ADV/LD
C
A1
D1
A0
D0
BURST
LOGIC
Q1 A1'
A0'
Q0
OE
CE1
CE2
CE3
ZZ
WRITE ADDRESS
REGISTER
READ LOGIC
INPUT E
REGISTER
O
U
T
P
U
T
B
U
F
F
E
R
S
E
SLEEP
CONTROL
ADV/LD
BW
A
BW
B
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
D
A
T
A
S
T
E
E
R
I
N
G
DQs
DQP
A
DQP
B
WE
OE
CE1
CE2
CE3
ZZ
INPUT
E
REGISTER
READ LOGIC
SLEEP
CONTROL
Document #: 38-05117 Rev. *C
Page 2 of 32
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CY7C1355B
CY7C1357B
Pin Configurations
100-lead TQFP
BW
B
BW
A
CE
1
CE
2
CE
3
V
DD
V
SS
NC / 18M
BW
D
BW
C
CEN
CLK
ADV/LD
WE
OE
A
82
100
A
99
A
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
A
BYTE C
BYTE D
DQP
C
DQ
C
DQ
C
V
DDQ
V
SS
DQ
C
DQ
C
DQ
C
DQ
C
V
SS
V
DDQ
DQ
C
DQ
C
V
SS
/ DNU
V
DD
NC
V
SS
DQ
D
DQ
D
V
DDQ
V
SS
DQ
D
DQ
D
DQ
D
DQ
D
V
SS
V
DDQ
DQ
D
DQ
D
DQP
D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
81
A
CY7C1355B
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
43
44
45
46
47
48
49
50
DQP
B
DQ
B
DQ
B
V
DDQ
V
SS
DQ
B
DQ
B
DQ
B
DQ
B
V
SS
V
DDQ
DQ
B
DQ
B
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SS
DQ
A
DQ
A
DQ
A
DQ
A
V
SS
V
DDQ
DQ
A
DQ
A
DQP
A
BYTE B
BYTE A
39
40
41
V
DD
A1
A0
NC / 288M
NC / 144M
V
SS
42
NC / 72M
NC / 36M
MODE
A
A
A
A
A
A
A
Document #: 38-05117 Rev. *C
A
A
A
A
Page 3 of 32
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CY7C1355B
CY7C1357B
Pin Configurations
(continued)
100-lead TQFP
BW
B
BW
A
CE
1
CE
2
CE
3
V
DD
V
SS
NC / 18M
CEN
CLK
ADV/LD
WE
NC
NC
OE
A
82
100
A
99
A
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
A
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQ
B
DQ
B
V
SS
V
DDQ
DQ
B
DQ
B
V
SS
/ DNU
V
DD
NC
V
SS
DQ
B
DQ
B
V
DDQ
V
SS
DQ
B
DQ
B
DQP
B
NC
V
SS
V
DDQ
NC
NC
NC
BYTE B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
81
A
CY7C1357B
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
43
44
45
46
47
48
49
50
A
NC
NC
V
DDQ
V
SS
NC
DQP
A
DQ
A
DQ
A
V
SS
V
DDQ
DQ
A
DQ
A
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SS
DQ
A
DQ
A
NC
NC
V
SS
V
DDQ
NC
NC
NC
BYTE A
39
40
41
V
DD
A1
A0
NC / 288M
NC / 144M
V
SS
42
NC / 72M
NC / 36M
MODE
A
A
A
A
A
A
A
Document #: 38-05117 Rev. *C
A
A
A
A
Page 4 of 32
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