CY7C1383BV25
CY7C1381BV25
512K x 36 / 1M x 18 Flow-Thru SRAM
Features
•
•
•
•
•
•
•
•
•
•
•
Fast access times: 7.5, 8.5, 10 ns
Fast clock speed: 117, 100, 83 MHz
Provide high-performance 2-1-1-1 access rate
Optimal for depth expansion
2.5V ± 5% power supply
Common data inputs and data outputs
Byte Write Enable and Global Write control
Chip enable for address pipeline
Address, data, and control registers
Internally self-timed Write Cycle
Burst control pins (interleaved or linear burst
sequence)
• Automatic power-down available using ZZ mode or CE
deselect
• High-density, high-speed packages
• JTAG boundary scan for BGA packaging version
registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE), Burst Control
Inputs (ADSC, ADSP, and ADV), Write Enables (BWa, BWb,
BWc, BWd,and BWe), and Global Write (GW).
Asynchronous inputs include the output enable (OE) and burst
mode control (MODE). The data outputs (Q), enabled by OE,
are also asynchronous.
Addresses and chip enables are registered with either
Address Status Processor (ADSP) or Address Status
Controller (ADSC) input pins. Subsequent burst addresses
can be internally generated as controlled by the Burst Advance
Pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles can be one
to four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa
controls DQ1–DQ8 and DP1. BWb controls DQ9–DQ16 and
DP2. BWc controls DQ17–DQ24and DP3. BWd controls
DQ25–DQ32 and DP4. BWa, BWb BWc, and BWd can be
active only with BWe being LOW. GW being LOW causes all
bytes to be written. WRITE pass-through capability allows
written data available at the output for the immediately next
Read cycle. This device also incorporates pipelined enable
circuit for easy depth expansion without penalizing system
performance.
All inputs and outputs of the CY7C1381BV25 and the
CY7C1383BV25 are JEDEC standard JESD8-5-compatible.
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low power CMOS designs using advanced single
layer polysilicon, three-layer metal technology. Each memory
cell consists of six transistors.
The CY7C1381BV25 and CY7C1383BV25 SRAMs integrate
524,288 × 36 and 1,048,576 × 18 SRAM cells with advanced
synchronous peripheral circuitry and a two-bit counter for
internal burst operation. All synchronous inputs are gated by
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
117 MHz
7.5
210
30
100 MHz
8.5
190
30
83 Mhz
10
160
30
Unit
ns
mA
mA
Commercial
Cypress Semiconductor Corporation
Document #: 38-05249 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised January 18, 2003
CY7C1383BV25
CY7C1381BV25
Functional Block Diagram
Logic Block Diagram ×18
MODE
(A
0
,A
1
) 2
CLK
ADV
ADSC
ADSP
A
[19:0]
GW
BWE
BWS b
BWS a
BURST Q0
CE COUNTER
Q1
CLR
Q
20
18
ADDRESS
CE REGISTER
D
D DQb[15:8],DP1Q
BYTEWRITE
REGISTERS
D DQa[7:0],DP0 Q
BYTEWRITE
REGISTERS
18
20
1M × 18
Memory
Array
CE1
CE2
CE3
18
D
ENABLE Q
CE REGISTER
CLK
18
INPUT
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQ
[15:0]
DP
[1:0]
Logic Block Diagram ×36
MODE
(A
0
,A
1
) 2
CLK
ADV
ADSC
ADSP
A
[18:0]
GW
BWE
BWS d
BWS c
BWS b
BWS a
CE1
CE2
CE3
BURST Q0
CE COUNTER
Q1
CLR
Q
19
17
ADDRESS
CE REGISTER
D
Q
D DQd[31:24],DP3
BYTEWRITE
REGISTERS
D DQc[23:16],DP2
Q
BYTEWRITE
REGISTERS
D DQb[15:8],DP1
Q
BYTEWRITE
REGISTERS
D DQa[7:0],DP0Q
BYTEWRITE
REGISTERS
D
ENABLE Q
CE REGISTER
CLK
INPUT
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQ
[31:0]
DP
[3:0]
17
19
512K × 36
Memory
Array
36
36
Document #: 38-05249 Rev. *A
Page 2 of 26
CY7C1383BV25
CY7C1381BV25
Pin Configurations
100-pin TQFP Packages
A
A
CE
1
CE
2
BWd
BWc
BWb
BWa
CE
3
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
A
A
CE
1
CE
2
NC
NC
BWb
BWa
CE
3
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
NC
NC
NC
V
DDQ
V
SSQ
NC
NC
DQb
DQb
V
SSQ
V
DDQ
DQb
DQb
NC
V
DD
NC
V
SS
DQb
DQb
V
DDQ
V
SSQ
DQb
DQb
DPb
NC
V
SSQ
V
DDQ
NC
NC
NC
DPc
DQc
DQc
V
DDQ
V
SSQ
DQc
DQc
DQc
DQc
V
SSQ
V
DDQ
DQc
DQc
NC
V
DD
NC
V
SS
DQd
DQd
V
DDQ
V
SSQ
DQd
DQd
DQd
DQd
V
SSQ
V
DDQ
DQd
DQd
DPd
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1381B
(512K × 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DPb
DQb
DQb
V
DDQ
V
SSQ
DQb
DQb
DQb
DQb
V
SSQ
V
DDQ
DQb
DQb
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DDQ
V
SSQ
DQa
DQa
DQa
DQa
V
SSQ
V
DDQ
DQa
DQa
DPa
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1383B
(1M × 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SSQ
NC
DPa
DQa
DQa
V
SSQ
V
DDQ
DQa
DQa
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DDQ
V
SSQ
DQa
DQa
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Document #: 38-05249 Rev. *A
MODE
A
A
A
A
A
1
A
0
NC
NC
V
SS
V
DD
A
A
A
A
A
A
A
A
A
MODE
A
A
A
A
A
1
A
0
NC
NC
V
SS
V
DD
A
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Page 3 of 26
CY7C1383BV25
CY7C1381BV25
Pin Configurations
(continued)
119-ball BGA
CY7C1381BV25 (512K × 36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQc
DQc
V
DDQ
DQc
DQc
V
DDQ
DQd
DQd
V
DDQ
DQd
DQd
NC
NC
V
DDQ
2
A
A
A
DQPc
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
DQPd
A
64M
TMS
3
A
A
A
V
SS
V
SS
V
SS
BWc
V
SS
NC
V
SS
BWd
V
SS
V
SS
V
SS
MODE
A
TDI
4
ADSP
ADSC
V
DD
NC
CE
1
OE
ADV
GW
V
DD
CLK
NC
BWE
A1
A0
V
DD
A
TCK
5
A
A
A
V
SS
V
SS
V
SS
BWb
V
SS
NC
V
SS
BWa
V
SS
V
SS
V
SS
NC
A
TDO
6
A
A
A
DQPb
DQb
DQb
DQb
DQb
V
DD
DQa
DQa
DQa
DQa
DQPa
A
32M
NC
7
V
DDQ
NC
NC
DQb
DQb
V
DDQ
DQb
DQb
V
DDQ
DQa
DQa
V
DDQ
DQa
DQa
NC
ZZ
V
DDQ
CY7C1383BV25 (1M × 18)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQb
NC
V
DDQ
NC
DQb
V
DDQ
NC
DQb
V
DDQ
DQb
NC
NC
64M
V
DDQ
2
A
A
A
NC
DQb
NC
DQb
NC
V
DD
DQb
NC
DQb
NC
DQPb
A
A
TMS
3
A
A
A
V
SS
V
SS
V
SS
BWb
V
SS
NC
V
SS
V
SS
V
SS
V
SS
V
SS
MODE
A
TDI
4
ADSP
ADSC
V
DD
NC
CE
1
OE
ADV
GW
V
DD
CLK
NC
BWE
A1
A0
V
DD
32M
TCK
5
A
A
A
V
SS
V
SS
V
SS
V
SS
V
SS
NC
V
SS
BWa
V
SS
V
SS
V
SS
NC
A
TDO
6
A
A
A
DQPa
NC
DQa
NC
DQb
V
DD
NC
DQa
NC
DQa
NC
A
A
NC
7
V
DDQ
NC
NC
NC
DQa
V
DDQ
DQa
NC
V
DDQ
DQa
NC
V
DDQ
NC
DQa
NC
ZZ
V
DDQ
Document #: 38-05249 Rev. *A
Page 4 of 26
CY7C1383BV25
CY7C1381BV25
Pin Configurations
(continued)
165-ball Bump FBGA
CY7C1381BV25 (512K × 36)–11 × 15 FBGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
DPc
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
DPd
NC
MODE
2
A
A
NC
DQc
DQc
DQc
DQc
V
SS
DQd
DQd
DQd
DQd
NC
64M
32M
3
CE
1
CE
2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
4
BWc
BWd
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
5
BWb
BWa
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
6
CE
3
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
A1
A0
7
BWE
GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
8
ADSC
OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
9
ADV
ADSP
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
10
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
11
NC
128M
DPb
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
DPa
A
A
CY7C1383BV25 (1M x 18) - 11 x 15 FBGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
NC
NC
NC
NC
NC
NC
DQb
DQb
DQb
DQb
DPb
NC
MODE
2
A
A
NC
DQb
DQb
DQb
DQb
V
SS
NC
NC
NC
NC
NC
64M
32M
3
CE
1
CE
2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
4
BWb
NC
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
5
NC
BWa
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
6
CE
3
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
A1
A0
7
BWE
GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
8
ADSC
OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
9
ADV
ADSP
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
10
A
A
NC
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
NC
A
A
11
A
128M
DPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
NC
NC
NC
A
A
Document #: 38-05249 Rev. *A
Page 5 of 26
