380B
CY7C1380B
CY7C1382B
512K x 36/1M x 18 Pipelined SRAM
Features
•
•
•
•
•
•
•
•
•
•
•
Fast clock speed: 200, 167, 150, 133 MHz
Provide high-performance 3-1-1-1 access rate
Fast OE access times: 3.0, 3.4, 3.8, and 4.2 ns
Optimal for depth expansion
3.3V (–5% / +10%) power supply
Common data inputs and data outputs
Byte Write Enable and Global Write control
Chip enable for address pipeline
Address, data, and control registers
Internally self-timed Write Cycle
Burst control pins (interleaved or linear burst se-
quence)
• Automatic power-down available using ZZ mode or CE
deselect
• High-density, high-speed packages
• JTAG boundary scan for BGA packaging version
isters controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE), burst control in-
puts (ADSC, ADSP, and ADV), write enables (BWa, BWb,
BWc, BWd and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and
burst mode control (MODE). DQ
a,b,c,d
and DP
a,b,c,d
apply to
CY7C1380B and DQ
a,b
and DP
a,b
apply to CY7C1382B. a, b,
c, d each are 8 bits wide in the case of DQ and 1 bit wide in
the case of DP.
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance Pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles can be one
to four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa
controls DQa and DPa. BWb controls DQb and DPb. BWc con-
trols DQc and DPc. BWd controls DQd and DPd. BWa, BWb,
BWc, and BWd can be active only with BWE being LOW. GW
being LOW causes all bytes to be written. WRITE
pass-through capability allows written data available at the out-
put for the immediately next READ cycle. This device also in-
corporates pipelined enable circuit for easy depth expansion
without penalizing system performance.
All inputs and outputs of the CY7C1380B and the CY7C1382B
are JEDEC standard JESD8-5 compatible.
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low-power CMOS designs using advanced sin-
gle-layer polysilicon, triple-layer metal technology. Each mem-
ory cell consists of six transistors.
The CY7C1380B and CY7C1382B SRAMs integrate
524,288x36 and 1,048,576x18 SRAM cells with advanced
synchronous peripheral circuitry and a 2-bit counter for inter-
nal burst operation. All synchronous inputs are gated by reg-
Selection Guide
200 MHz
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Commercial
3.0
315
20
167 MHz
3.4
285
20
150 MHz
3.8
265
20
133 MHz
4.2
245
20
Cypress Semiconductor Corporation
Document #: 38-05267 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised October 8, 2001
CY7C1380B
CY7C1382B
Logic Block Diagram CY7C1380B - 512K x 36
MODE
(A
[1;0]
) 2
CLK
ADV
ADSC
ADSP
A
[18:0]
GW
BWE
BW
d
BW
c
D
BW
b
D
BW
a
CE
1
CE
2
CE
3
D
BURST Q
0
CE COUNTER
Q
1
CLR
Q
19
17
D
ADDRESS
CE REGISTER
D
DQ
d
, DP
d
BYTEWRITE
REGISTERS
DQ
c
, DP
c
BYTEWRITE
REGISTERS
DQ
b
, DP
b
BYTEWRITE
REGISTERS
DQ
a
, DP
a
BYTEWRITE
REGISTERS
ENABLE CE
REGISTER
Q
17
19
512KX36
MEMORY
ARRAY
D
Q
Q
Q
36
Q
36
D ENABLE DELAY Q
REGISTER
OE
ZZ
SLEEP
CONTROL
OUTPUT
REGISTERS
CLK
INPUT
REGISTERS
CLK
DQ
a,b,c,d
DP
a,b
Logic Block Diagram CY7C1382B - 1M x 18
MODE
(A
[1;0]
) 2
CLK
ADV
ADSC
ADSP
A
[19:0]
GW
BWE
BW
b
BW
a
BURST Q
0
CE COUNTER
Q
1
CLR
Q
19
17
D
ADDRESS
CE REGISTER
D
DQ
b
, DP
b
BYTEWRITE
REGISTERS
DQ
a
, DP
a
BYTEWRITE
REGISTERS
Q
17
19
1M X 18
MEMORY
ARRAY
D
Q
CE
1
CE
2
CE
3
18
D
ENABLE CE
CE REGISTER
Q
18
D ENABLE DELAY Q
REGISTER
OE
ZZ
SLEEP
CONTROL
OUTPUT
REGISTERS
CLK
INPUT
REGISTERS
CLK
DQ
a,b
DP
a,b
Document #: 38-05267 Rev. *A
Page 2 of 34
CY7C1380B
CY7C1382B
Pin Configurations
100-Pin TQFP
(Top View)
A
A
CE
1
CE
2
BWd
BWc
BWb
BWa
CE
3
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
DQPc
DQc
DQc
V
DDQ
V
SSQ
DQc
DQc
DQc
DQc
V
SSQ
V
DDQ
DQc
DQc
NC
V
DD
NC
V
SS
DQd
DQd
V
DDQ
V
SSQ
DQd
DQd
DQd
DQd
V
SSQ
V
DDQ
DQd
DQd
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1380B
(512K X 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb NC
NC
DQb
NC
DQb
V
DDQ
V
DDQ
V
SSQ
V
SSQ
NC
DQb
NC
DQb
DQb DQb
DQb DQb
V
SSQ
V
SSQ
V
DDQ
V
DDQ
DQb DQb
DQb DQb
NC
V
SS
V
DD
NC
NC
V
DD
V
SS
ZZ
DQa DQb
DQa DQb
V
DDQ
V
DDQ
V
SSQ
V
SSQ
DQa DQb
DQa DQb
DQa DPb
NC
DQa
V
SSQ
V
SSQ
V
DDQ
V
DDQ
NC
DQa
NC
DQa
DQPa NC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE
1
CE
2
NC
NC
BWb
BWa
CE
3
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1382B
(1M x 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SSQ
NC
DPa
DQa
DQa
V
SSQ
V
DDQ
DQa
DQa
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DDQ
V
SSQ
DQa
DQa
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
MODE
A
A
A
A
A
1
A
0
NC
NC
V
SS
V
DD
A
A
A
A
A
A
A
A
A
MODE
A
A
A
A
A
1
A
0
NC
NC
V
SS
V
DD
Document #: 38-05267 Rev. *A
A
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Page 3 of 34
CY7C1380B
CY7C1382B
Pin Configurations
(continued)
CY7C1380B (512K x 36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQc
DQc
V
DDQ
DQc
DQc
V
DDQ
DQd
DQd
V
DDQ
DQd
DQd
NC
NC
V
DDQ
2
A
A
A
DPc
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
DPd
A
64M
TMS
3
A
A
A
V
SS
V
SS
V
SS
BWc
V
SS
NC
V
SS
BWd
V
SS
V
SS
V
SS
MODE
A
TDI
4
ADSP
ADSC
V
DD
NC
CE
1
OE
ADV
GW
V
DD
CLK
NC
BWE
A1
A0
V
DD
A
TCK
5
A
A
A
V
SS
V
SS
V
SS
BWb
V
SS
NC
V
SS
BWa
V
SS
V
SS
V
SS
V
DD
A
TDO
6
A
A
A
DPb
DQb
DQb
DQb
DQb
V
DD
DQa
DQa
DQa
DQa
DPa
A
32M
NC
7
V
DDQ
NC
NC
DQb
DQb
V
DDQ
DQb
DQb
V
DDQ
DQa
DQa
V
DDQ
DQa
DQa
NC
ZZ
V
DDQ
CY7C1382B (1M x 18)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQb
NC
V
DDQ
NC
DQb
V
DDQ
NC
DQb
V
DDQ
DQb
NC
NC
64M
V
DDQ
2
A
A
A
NC
DQb
NC
DQb
NC
V
DD
DQb
NC
DQb
NC
DPb
A
A
TMS
3
A
A
A
V
SS
V
SS
V
SS
BWb
V
SS
NC
V
SS
V
SS
V
SS
V
SS
V
SS
MODE
A
TDI
4
ADSP
ADSC
V
DD
NC
CE
1
OE
ADV
GW
V
DD
CLK
NC
BWE
A1
A0
V
DD
32M
TCK
5
A
A
A
V
SS
V
SS
V
SS
V
SS
V
SS
NC
V
SS
BWa
V
SS
V
SS
V
SS
V
DD
A
TDO
6
A
A
A
DPa
NC
DQa
NC
DQa
V
DD
NC
DQa
NC
DQa
NC
A
A
NC
7
V
DDQ
NC
NC
NC
DQa
V
DDQ
DQa
NC
V
DDQ
DQa
NC
V
DDQ
NC
DQa
NC
ZZ
V
DDQ
Document #: 38-05267 Rev. *A
Page 4 of 34
CY7C1380B
CY7C1382B
Pin Configurations
(continued)
165-Ball Bump FBGA
CY7C1380B (512K x 36) - 11 x 15 FBGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
DPc
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
DPd
NC
MODE
2
A
A
NC
DQc
DQc
DQc
DQc
V
SS
DQd
DQd
DQd
DQd
NC
64M
32M
3
CE
1
CE
2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
4
BWc
BWd
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
5
BWb
BWa
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
6
CE
3
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
A1
A0
7
BWE
GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
TDO
TCK
8
ADSC
OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
9
ADV
ADSP
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
10
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
11
NC
128M
DPb
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
DPa
A
A
CY7C1382B (1M x 18) - 11 x 15 FBGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
NC
NC
NC
NC
NC
V
DD
DQb
DQb
DQb
DQb
DPb
NC
MODE
2
A
A
NC
DQb
DQb
DQb
DQb
V
SS
NC
NC
NC
NC
NC
64M
32M
3
CE
1
CE
2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
4
BWb
NC
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
5
NC
BWa
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
6
CE
3
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
A1
A0
7
BWE
GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
TDO
TCK
8
ADSC
OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
9
ADV
ADSP
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
10
A
A
NC
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
NC
A
A
11
A
128M
DPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
NC
NC
NC
A
A
Document #: 38-05267 Rev. *A
Page 5 of 34
