PRELIMINARY
CY7C1392V18
CY7C1393V18
CY7C1394V18
18-Mb DDR-II SIO SRAM Two-word
Burst Architecture
Features
• 18-Mb density (2M x 8, 1M x 18, 512K x 36)
— Supports concurrent transactions
• 250-MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces (data transferred at
500 MHz) @ 250 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two output clocks (C and C) accounts for clock skew
and flight time mismatches
• Echo clocks (CQ and CQ) simplify data capture in high
speed systems
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• 1.8V core power supply with HSTL inputs and outputs
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–1.9V)
• 13x15 mm 1.0-mm pitch fBGA package, 165 ball (11 x 15
matrix)
• JTAG Interface
• On-chip Delay Lock Loop (DLL)
Functional Description
The CY7C1392V18/CY7C1393V18/CY7C1394V18 are 1.8V
Synchronous Pipelined SRAMs equipped with DDR-II SIO
(Double Data Rate Separate I/O) architecture. The DDR-II SIO
consists of two separate DDR ports, Read and Write port, to
access the memory array. The Read port has dedicated
outputs and the Write port has dedicated inputs to support
read and write operations concurrently. Access to each port is
accomplished using a common address bus. Addresses for
Read and Write are latched on alternate rising edges of the
input (K) clock. Write data is registered on the rising edges of
both K and K. Read data is driven on the rising edges of C and
C if provided, or on the rising edge of K and K if C/C are not
provided. Each address location is associated with two 8-bit
words in the case of CY7C1392V18, two 18-bit words in the
case of CY7C1393V18, and two 36-bit words in the case of
CY7C1394V18, that burst sequentially into or out of the
device.
Asynchronous inputs include impedance match (ZQ).
Synchronous data outputs are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR-II SIO SRAM in the
system design. Output data clocks (C/C) enable maximum
system clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled
by the K/K input clocks. All data outputs pass through output
registers controlled by the C/C input clocks (or K/K in single
clock mode). Writes are conducted with on-chip synchronous
self-timed write circuitry.
Configuration
CY7C1392V18–2M x 8
CY7C1393V18–1M x18
CY7C1394V18–512K x 36
Logic Block Diagram (CY7C1392V18)
D
[7:0]
8
Write
Data Reg
Write Add. Decode
Write
Data Reg
Read Add. Decode
A
(19:0)
20
Address
Register
K
K
1M x 8
Memory
Array
1M x 8
Memory
Array
CLK
Gen.
Control
Logic
Read Data Reg.
R/W
V
REF
LD
BWS
0
BWS
1
16
Control
Logic
8
Reg.
8
Reg.
8
LD
R/W
C
C
CQ
CQ
Reg. 8
8
Q
[7:0]
Cypress Semiconductor Corporation
Document #: 38-05179 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised July 31, 2002
PRELIMINARY
Logic Block Diagram (CY7C1393V18)
D
[17:0]
18
CY7C1392V18
CY7C1393V18
CY7C1394V18
19
Write Add. Decode
K
K
512K x 18 512K x 18
Memory
Memory
Array
Array
Read Add. Decode
A
(18:0)
Address
Register
Write
Data Reg
Write
Data Reg
CLK
Gen.
Control
Logic
Read Data Reg.
R/W
V
REF
LD
BWS
0
BWS
1
36
Control
Logic
18
Reg.
18
Reg.
18
LD
R/W
C
C
CQ
CQ
Reg. 18
18
Q
[17:0]
Logic Block Diagram (CY7C1394V18)
D
[35:0]
36
18
Write Add. Decode
K
K
256K x 36 256K x 36
Memory
Memory
Array
Array
Read Add. Decode
A
(17:0)
Address
Register
Write
Data Reg
Write
Data Reg
CLK
Gen.
Control
Logic
Read Data Reg.
R/W
V
REF
LD
BWS
[3:0]
72
Control
Logic
36
Reg.
36
Reg.
36
LD
R/W
C
C
CQ
CQ
Reg. 36
36
Q
[35:0]
Selection Guide
300 MHz
[1]
Maximum Operating Frequency
Maximum Operating Current
Note:
1. Shaded cells indicate advanced information.
250 MHz
250
TBD
200 MHz
200
TBD
167 MHz
167
TBD
Unit
MHz
mA
300
TBD
Document #: 38-05179 Rev. *A
Page 2 of 24
PRELIMINARY
Pin Configurations
CY7C1392V18 (2M x 8) - 11 x 15 FBGA
CY7C1392V18
CY7C1393V18
CY7C1394V18
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
/72M
NC
NC
D4
NC
NC
D5
V
REF
NC
NC
Q6
NC
D7
NC
TCK
3
A
NC
NC
NC
Q4
NC
Q5
V
DDQ
NC
NC
D6
NC
NC
Q7
A
4
R/W
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
1
NC
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
NC
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
LD
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
V
DD
/36M
NC
NC
NC
D2
NC
NC
V
REF
Q1
NC
NC
NC
NC
NC
TMS
11
CQ
Q3
D3
NC
Q2
NC
NC
ZQ
D1
NC
Q0
D0
NC
NC
TDI
CY7C1393V18 (1M x 18) - 11 x 15 FBGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
Q9
NC
D11
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
3
D9
D10
Q10
Q11
D12
Q13
V
DDQ
D14
Q14
D15
D16
Q16
Q17
A
4
R/W
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
1
NC
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
NC
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
LD
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
GND/72M
NC
Q7
NC
D6
NC
NC
V
REF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
V
SS
/144M NC/36M
Document #: 38-05179 Rev. *A
Page 3 of 24
PRELIMINARY
Pin Configurations
(continued)
CY7C1394V18 (512K x 36) - 11 x 15 FBGA
CY7C1392V18
CY7C1393V18
CY7C1394V18
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
Q27
D27
D28
Q29
Q30
D30
DOFF
D31
Q32
Q33
D33
D34
Q35
TDO
2
Q18
Q28
D20
D29
Q21
D22
V
REF
Q31
D32
Q24
Q34
D26
D35
TCK
3
D18
D19
Q19
Q20
D21
Q22
V
DDQ
D23
Q23
D24
D25
Q25
Q26
A
4
R/W
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
2
BWS
3
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
BWS
1
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
LD
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
D17
D16
Q16
Q15
D14
Q13
V
DDQ
D12
Q12
D11
D10
Q10
Q9
A
10
Q17
Q7
D15
D6
Q14
D13
V
REF
Q4
D3
Q11
Q1
D9
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
V
SS
/288M NC/72M
NC/36M V
SS
/144M
Pin Definitions
Pin Name
D
[x:0]
I/O
Input-
Synchronous
Pin Description
Data input signals, sampled on the rising edge of K and K clocks during valid write
operations.
CY7C1392V18
−
DQ
[7:0]
CY7C1393V18
−
DQ
[17:0]
CY7C1394V18
−
DQ
[35:0]
Synchronous Load:
This input is brought LOW when a bus cycle sequence is to be
defined. This definition includes address and read/write direction. All transactions
operate on a burst of 2 data (one period of bus activity).
Byte Write Select 0, 1, 2, and 3
−
active LOW.
Sampled on the rising edge of the K and
K clocks during write operations. Used to select which byte is written into the device
during the current portion of the write operations. Bytes not written remain unaltered.
CY7C1392V18
−
BWS
0
controls D
[3:0]
and BWS
1
controls D
[7:4]
.
CY7C1393V18
−
BWS
0
controls D
[8:0]
and BWS
1
controls D
[17:9].
CY7C1394V18
−
BWS
0
controls D
[8:0]
, BWS
1
controls D
[17:9]
, BWS
2
controls D
[26:18]
and
BWS
3
controls D
[35:27]
All the byte writes are sampled on the same edge as the data. Deselecting a Byte Write
Select will cause the corresponding byte of data to be ignored and not written into the
device.
Address Inputs.
Sampled on the rising edge of the K clock during active read and write
operations. These address inputs are multiplexed for both Read and Write operations.
Internally, the device is organized as 2M x 8 (2 arrays each of 1M x 8) for CY7C1392V18,
1M x 18 (2 arrays each of 512K x 18) for CY7C1393V18 and 512K x 36 (2 arrays each
of 256K x 36) for CY7C1394V18.
All the address inputs are ignored when the appropriate port is deselected.
Data Output signals.
These pins drive out the requested data during a Read operation.
Valid data is driven out on the rising edge of both the C and C clocks during Read
operations or K and K when in single clock mode. When the Read port is deselected,
Q
[x:0]
are automatically three-stated.
LD
Input-
Synchronous
Input-
Synchronous
BWS
[3:0]
A
Input-
Synchronous
Q
[x:0]
Outputs-
Synchronous
Document #: 38-05179 Rev. *A
Page 4 of 24
PRELIMINARY
Pin Definitions
(continued)
Pin Name
R/W
I/O
Input-
Synchronous
Input-
Clock
Input-
Clock
Input-
Clock
Input-
Clock
Input-
Clock
Input-Clock
Pin Description
CY7C1392V18
CY7C1393V18
CY7C1394V18
Synchronous Read/Write Input: When LD is LOW, this input designates the access
type (Read when R/W is HIGH, Write when R/W is LOW) for loaded address.
R/W
must meet the set-up and hold times around edge of K.
Positive Output Clock Input.
C is used in conjunction with C to clock out the Read data
from the device. C and C can be used together to deskew the flight times of various
devices on the board back to the controller. See application example for further details.
Negative Output Clock Input.
C is used in conjunction with C to clock out the Read data
from the device. C and C can be used together to deskew the flight times of various
devices on the board back to the controller. See application example for further details.
Positive Input Clock Input.
The rising edge of K is used to capture synchronous inputs
to the device and to drive out data through Q
[x:0]
when in single clock mode. All accesses
are initiated on the rising edge of K.
Negative Input Clock Input.
K is used to capture synchronous inputs being presented
to the device and to drive out data through Q
[x:0]
when in single clock mode.
Positive Output Echo Clock.
The rising edge of CQ is synchronous with respect to C
(or K in single clock mode) and is used for data valid indication coming off of C (or K)
clock. This is a free-running clock.
Negative Output Echo Clock.
The rising edge of CQ is synchronous with respect to C
(or K in single clock mode) and is used for data valid indication coming off of C (or K)
clock. This is a free-running clock.
Output Impedance Matching Input.
This input is used to tune the device outputs to the
system data bus impedance. Q
[x:0]
output impedance are set to 0.2 x RQ, where RQ is
a resistor connected between ZQ and ground. Alternately, this pin can be connected
directly to V
DD
, which enables the minimum impedance mode. This pin cannot be
connected directly to GND or left unconnected.
DLL Turn Off.
Connecting this pin to ground will turn off the DLL inside the device. The
timings in the DLL turned off operation will be different from those listed in this data sheet.
More details on this operation can be found in the application note, “DLL Operation in
the QDR
TM
-II.”
TDO for JTAG.
TCK pin for JTAG.
TDI pin for JTAG.
TMS pin for JTAG.
Address expansion for 36M.
This is a No connect on the 18M and could be tied to any
level on the 18M devices
Address expansion for 36M.
This should be tied LOW on the 18M devices.
Address expansion for 72M.
This is a No connect on the 18M and could be tied to any
level on the 18M devices
Address expansion for 72M.
This must be tied LOW on the 18M SRAM.
Address expansion for 144M.
This must be tied LOW on the 18M SRAM.
Address expansion for 288M.
This must be tied LOW on the 18M SRAM.
Reference Voltage Input.
Static input used to set the reference level for HSTL inputs
and Outputs as well as A/C measurement points.
Power supply inputs to the core of the device.
Should be connected to 1.8V power
supply.
Ground for the device.
Should be connected to ground of the system.
Power supply inputs for the outputs of the device.
Should be connected to 1.5V
power supply.
No connect.
C
C
K
K
CQ
CQ
ZQ
Input
DOFF
Input
TDO
TCK
TDI
TMS
NC/36M
GND/36M
NC/72M
V
SS
/72M
V
SS
/144M
V
SS
/288M
V
REF
V
DD
V
SS
V
DDQ
NC
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input-
Reference
Power Supply
Ground
Power Supply
NC
Document #: 38-05179 Rev. *A
Page 5 of 24
嵌入式系统
