is provided by an active LOW Chip Enable (CE) and active
LOW Output Enable (OE) and three-state drivers. The device
has an automatic power-down feature, reducing the power
consumption by more than 95% when deselected.
An active LOW Write Enable signal (WE) controls the writing/
reading operation of the memory. When CE and WE inputs
are both LOW, data on the eight data input/output pins (I/O
0
through I/O
7
) is written into the memory location addressed by
the address present on the address pins (A
0
through A
14
).
Reading the device is accomplished by selecting the device
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the con-
tents of the location addressed by the information on address
pins is present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. The CY7C1399 is available in 28-pin standard
300-mil-wide SOJ and TSOP Type I packages.
Functional Description
The CY7C1399 is a high-performance 3.3V CMOS Static RAM
organized as 32,768 words by 8 bits. Easy memory expansion
Logic Block Diagram
Pin Configurations
SOJ
Top View
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
A
4
A
3
A
2
A
1
OE
A
0
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
INPUT BUFFER
I/O
0
I/O
1
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
CE
WE
OE
ROW DECODER
I/O
2
SENSE AMPS
32K x 8
ARRAY
I/O
3
I/O
4
C1399–2
I/O
5
COLUMN
DECODER
POWER
DOWN
I/O
6
I/O
7
A
10
A
11
A
12
A
13
A
14
C1399–1
Selection Guide
7C1399–12
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (µA)
Maximum CMOS Standby Current (µA) L
12
60
500
50
7C1399–15
15
55
500
50
7C1399–20
20
50
500
50
7C1399–25
25
45
500
50
7C1399–35
35
40
500
50
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
March 25, 1999
CY7C1399
Pin Configuration
TSOP
Top View
OE
A
1
A
2
A
3
A
4
WE
V
CC
A
5
A
6
A
7
A
8
A
9
A
10
A
11
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
A
0
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
14
A
13
A
12
C1399–3
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................. –55°C to +125°C
Supply Voltage on V
CC
to Relative GND
[1]
.... –0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State
[1]
....................................–0.5V to V
CC
+ 0.5V
DC Input Voltage
[1]
.................................–0.5V to V
CC
+ 0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0
°
C to +70
°
C
–40
°
C to +85
°
C
V
CC
3.3V
±300
mV
3.3V
±300
mV
Electrical Characteristics
Over the Operating Range
[1]
7C1399–12
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
I
SB1
I
SB2
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage
Current
Output Short
Circuit Current
[2]
V
CC
Operating
Supply Current
GND
≤
V
I
≤
V
CC
,
Output Disabled
V
CC
= Max., V
OUT
= GND
V
CC
= Max., I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
L
Test Conditions
V
CC
= Min., I
OH
= –2.0 mA
V
CC
= Min., I
OL
= 4.0 mA
2.2
–0.3
–1
–5
Min.
2.4
0.4
V
CC
+0.3V
0.8
+1
+5
–300
60
5
3
500
50
2.2
–0.3
–1
–5
Max.
7C1399–15
Min.
2.4
0.4
V
CC
+0.3V
0.8
+1
+5
–300
55
5
3
500
50
2.2
–0.3
–1
–5
Max.
7C1399–20
Min.
2.4
0.4
V
CC
+0.3V
0.8
+1
+5
–300
50
5
3
500
50
µA
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
Automatic CE Power-Down Max. V
CC
, CE
≥
V
IH
,
Current — TTL Inputs
V
IN
≥
V
IH
, or V
IN
≤
V
IL
,f = f
MAX
Automatic CE Power-Down Max. V
CC
, CE
≥
V
CC
– 0.3V, V
IN
≥
Current — CMOS Inputs
[3]
V
CC
– 0.3V, or V
IN
≤
0.3V,
L
WE
≥V
CC
– 0.3V or WE
≤0.3V,
f=f
MAX
Notes:
1. Minimum voltage is equal to – 2.0V for pulse durations of less than 20 ns.
2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
3. Device draws low standby current regardless of switching on the addresses.
2
CY7C1399
Electrical Characteristics
Over the Operating Range(continued)
7C1399–25
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
I
SB1
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
Output Short Circuit
Current
[2]
V
CC
Operating
Supply Current
Automatic CE Power-Down
Current — TTL Inputs
Automatic CE Power-Down
Current — CMOS Inputs
[3]
GND
≤
V
I
≤
V
CC
,
Output Disabled
V
CC
= Max., V
OUT
= GND
V
CC
= Max., I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Max. V
CC
, CE
≥
V
IH
,
V
IN
≥
V
IH
, or V
IN
≤
V
IL
,
f = f
MAX
Max. V
CC
, CE
≥
V
CC
–0.3V, V
IN
≥
V
CC
– 0.3V, or V
IN
≤
0.3V,
WE≥V
CC
–0.3V or WE≤ 0.3V,
f=f
MAX
L
Test Conditions
V
CC
= Min., I
OH
= –2.0 mA
V
CC
= Min., I
OL
= 4.0 mA
2.2
–0.3
–1
–5
Min.
2.4
0.4
V
CC
+0.3V
0.8
+1
+5
–300
45
5
3
500
L
50
2.2
–0.3
–1
–5
Max.
7C1399–35
Min.
2.4
0.4
V
CC
+0.3V
0.8
+1
+5
–300
40
5
3
500
50
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
mA
µA
µA
I
SB2
Capacitance
[4]
Parameter
C
IN
: Addresses
C
IN
: Controls
C
OUT
Output Capacitance
Description
Input Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz, V
CC
= 3.3V
Max.
5
6
6
Unit
pF
pF
pF
AC Test Loads and Waveforms
R1 317Ω
3.3V
OUTPUT
C
L
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
167Ω
OUTPUT
1.73V
R2
351Ω
3.0V
10%
GND
≤
3 ns
ALL INPUT PULSES
90%
90%
10%
≤
3 ns
C1399–4
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
3
CY7C1399
Switching Characteristics
Over the Operating Range
[5]
7C1399–12
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[6]
OE HIGH to High Z
[6, 7]
CE LOW to Low Z
[6]
7C1399–15
Min.
15
Max.
7C1399–20
Min.
20
Max.
7C1399–25
Min.
25
Max.
7C1399–35
Min.
35
Max.
Unit
ns
35
3
35
10
0
7
3
8
0
35
35
20
20
0
0
20
12
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
3
ns
ns
Description
Min.
12
Max.
12
3
12
5
0
5
3
6
0
12
12
8
8
0
0
8
7
0
7
3
3
15
10
10
0
0
10
8
0
0
3
0
3
15
3
15
6
0
6
3
7
0
15
20
12
12
0
0
12
10
0
7
3
20
3
20
7
0
6
3
7
0
20
25
15
15
0
0
15
11
0
7
3
25
25
8
7
8
25
CE HIGH to High Z
[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z
[8]
WE HIGH to Low Z
[6]
WRITE CYCLE
[8, 9]
7
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
t
CDR[4]
t
R[4]
Description
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
V
CC
= V
DR
= 2.0V,
CE > V
CC
– 0.3V,
L
V
IN
> V
CC
– 0.3V or
V
IN
< 0.3V
Conditions
Min.
2.0
200
20
0
t
RC
Max.
Unit
V
µA
µA
ns
ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and capacitance C
L
= 30 pF.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7. t
HZOE
, t
HZCE
, t
HZWE
are specified with C
L
= 5 pF as in AC Test Loads. Transition is measured ±500 mV from steady state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
4
CY7C1399
Data Retention Waveform
DATA RETENTION MODE
V
CC
3.0V
t
CDR
CE
C1399–5
V
DR
≥
2V
3.0V
t
R
Switching Waveforms
Read Cycle No. 1
[10, 11]
t
RC
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID
t
AA
DATA VALID
C1399–6
Read Cycle No. 2
[11, 12]
CE
t
ACE
OE
t
DOE
t
LZOE
HIGH IMPEDANCE
t
LZCE
V
CC
SUPPLY
CURRENT
t
PU
50%
t
PD
ICC
50%
ISB
C1399–7
t
RC
t
HZOE
t
HZCE
DATA VALID
HIGH
IMPEDANCE
DATA OUT
Notes:
10. Device is continuously selected. OE, CE = V
IL
.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
