CY7C1411BV18, CY7C1426BV18
CY7C1413BV18, CY7C1415BV18
36-Mbit QDR™-II SRAM 4-Word
Burst Architecture
Features
■
Configurations
CY7C1411BV18 – 4M x 8
CY7C1426BV18 – 4M x 9
CY7C1413BV18 – 2M x 18
CY7C1415BV18 – 1M x 36
Separate independent read and write data ports
❐
Supports concurrent transactions
300 MHz clock for high bandwidth
4-word burst for reducing address bus frequency
Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 600 MHz) at 300 MHz
Two input clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
Single multiplexed address input bus latches address inputs
for both read and write ports
Separate port selects for depth expansion
Synchronous internally self-timed writes
QDR-II operates with 1.5 cycle read latency when DLL is
enabled
Operates as a QDR-I device with 1 cycle read latency in DLL
off mode
Available in x 8, x 9, x 18, and x 36 configurations
Full data coherency, providing most current data
Core V
DD
= 1.8 (±0.1V); IO V
DDQ
= 1.4V to V
DD
Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)
Offered in both Pb-free and non Pb-free packages
Variable drive HSTL output buffers
JTAG 1149.1 compatible test access port
Delay Lock Loop (DLL) for accurate data placement
■
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Functional Description
The CY7C1411BV18, CY7C1426BV18, CY7C1413BV18, and
CY7C1415BV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR™-II architecture. QDR-II architecture
consists of two separate ports to access the memory array. The
read port has dedicated data outputs to support the read opera-
tions and the write port has dedicated data inputs to support the
write operations. QDR-II architecture has separate data inputs
and data outputs to completely eliminate the need to
“turn-around” the data bus required with common IO devices.
Access to each port is through a common address bus.
Addresses for read and write addresses are latched on alternate
rising edges of the input (K) clock. Accesses to the QDR-II read
and write ports are completely independent of one another. To
maximize data throughput, read and write ports are equipped
with DDR interfaces. Each address location is associated with
four
8-bit
words
(CY7C1411BV18),
9-bit
words
(CY7C1426BV18), 18-bit words (CY7C1413BV18), or 36-bit
words (CY7C1415BV18) that burst sequentially into or out of the
device. Because data can be transferred into and out of the
device on every rising edge of both input clocks (K and K and C
and C), memory bandwidth is maximized while simplifying
system design by eliminating bus “turn-arounds.”
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on chip
synchronous self-timed write circuitry.
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Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
x8
x9
x18
x36
300 MHz
300
930
940
1020
1230
278 MHz
278
865
870
950
1140
250 MHz
250
790
795
865
1040
200 MHz
200
655
660
715
850
167 MHz
167
570
575
615
725
Unit
MHz
mA
Cypress Semiconductor Corporation
Document Number: 001-07037 Rev. *C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised September 27, 2007
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CY7C1411BV18, CY7C1426BV18
CY7C1413BV18, CY7C1415BV18
Logic Block Diagram (CY7C1411BV18)
D
[7:0]
8
Write
Reg
Write
Reg
Write
Reg
Write
Reg
Read Add. Decode
Write Add. Decode
A
(19:0)
20
Address
Register
Address
Register
20
A
(20:0)
1M x 8 Array
1M x 8 Array
1M x 8 Array
1M x 8 Array
K
K
CLK
Gen.
RPS
Control
Logic
C
C
CQ
DOFF
Read Data Reg.
32
V
REF
WPS
NWS
[1:0]
Control
Logic
16
16
Reg.
Reg.
Reg. 8
8
8
8
CQ
8
Q
[7:0]
Logic Block Diagram (CY7C1426BV18)
D
[8:0]
9
Write
Reg
Write
Reg
Write
Reg
Write
Reg
Read Add. Decode
Write Add. Decode
A
(19:0)
20
Address
Register
Address
Register
20
A
(19:0)
1M x 9 Array
1M x 9 Array
1M x 9 Array
1M x 9 Array
K
K
CLK
Gen.
RPS
Control
Logic
C
C
CQ
DOFF
Read Data Reg.
36
V
REF
WPS
BWS
[0]
Control
Logic
18
18
Reg.
Reg.
Reg. 9
9
9
9
CQ
9
Q
[8:0]
Document Number: 001-07037 Rev. *C
Page 2 of 30
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CY7C1411BV18, CY7C1426BV18
CY7C1413BV18, CY7C1415BV18
Logic Block Diagram (CY7C1413BV18)
D
[17:0]
18
Write
Reg
Write
Reg
Write
Reg
Write
Reg
Read Add. Decode
Write Add. Decode
A
(18:0)
19
Address
Register
Address
Register
19
A
(18:0)
512K x 18 Array
512K x 18 Array
512K x 18 Array
512K x 18 Array
K
K
CLK
Gen.
RPS
Control
Logic
C
C
CQ
DOFF
Read Data Reg.
72
V
REF
WPS
BWS
[1:0]
Control
Logic
36
36
Reg.
Reg.
Reg. 18
18
18
18
CQ
18
Q
[17:0]
Logic Block Diagram (CY7C1415BV18)
D
[35:0]
36
Write
Reg
Write
Reg
Write
Reg
Write
Reg
Read Add. Decode
Write Add. Decode
A
(17:0)
18
Address
Register
Address
Register
18
A
(17:0)
256K x 36 Array
256K x 36 Array
256K x 36 Array
256K x 36 Array
K
K
CLK
Gen.
RPS
Control
Logic
C
C
CQ
DOFF
Read Data Reg.
144
V
REF
WPS
BWS
[3:0]
Control
Logic
72
72
Reg.
Reg.
Reg. 36
36
36
36
CQ
36
Q
[35:0]
Document Number: 001-07037 Rev. *C
Page 3 of 30
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CY7C1411BV18, CY7C1426BV18
CY7C1413BV18, CY7C1415BV18
Pin Configuration
The pin configuration for CY7C1411BV18, CY7C1426BV18, CY7C1413BV18, and CY7C1415BV18 follow.
[1]
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1411BV18 (4M x 8)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/72M
NC
NC
D4
NC
NC
D5
V
REF
NC
NC
Q6
NC
D7
NC
TCK
3
A
NC
NC
NC
Q4
NC
Q5
V
DDQ
NC
NC
D6
NC
NC
Q7
A
4
WPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
NWS
1
NC/288M
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
NC/144M
NWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
RPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
A
NC
NC
NC
D2
NC
NC
V
REF
Q1
NC
NC
NC
NC
NC
TMS
11
CQ
Q3
D3
NC
Q2
NC
NC
ZQ
D1
NC
Q0
D0
NC
NC
TDI
CY7C1426BV18 (4M x 9)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/72M
NC
NC
D5
NC
NC
D6
V
REF
NC
NC
Q7
NC
D8
NC
TCK
3
A
NC
NC
NC
Q5
NC
Q6
V
DDQ
NC
NC
D7
NC
NC
Q8
A
4
WPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
NC
NC/288M
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
NC/144M
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
RPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
A
NC
NC
NC
D3
NC
NC
V
REF
Q2
NC
NC
NC
NC
D0
TMS
11
CQ
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
Note
1. NC/72M, NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-07037 Rev. *C
Page 4 of 30
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CY7C1411BV18, CY7C1426BV18
CY7C1413BV18, CY7C1415BV18
Pin Configuration
(continued)
The pin configuration for CY7C1411BV18, CY7C1426BV18, CY7C1413BV18, and CY7C1415BV18 follow.
[1]
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1413BV18 (2M x 18)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/144M
Q9
NC
D11
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
3
A
D9
D10
Q10
Q11
D12
Q13
V
DDQ
D14
Q14
D15
D16
Q16
Q17
A
4
WPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
1
NC
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
NC/288M
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
RPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
NC/72M
NC
Q7
NC
D6
NC
NC
V
REF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
CY7C1415BV18 (1M x 36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
Q27
D27
D28
Q29
Q30
D30
DOFF
D31
Q32
Q33
D33
D34
Q35
TDO
2
Q18
Q28
D20
D29
Q21
D22
V
REF
Q31
D32
Q24
Q34
D26
D35
TCK
3
D18
D19
Q19
Q20
D21
Q22
V
DDQ
D23
Q23
D24
D25
Q25
Q26
A
4
WPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
2
BWS
3
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
BWS
1
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
RPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
D17
D16
Q16
Q15
D14
Q13
V
DDQ
D12
Q12
D11
D10
Q10
Q9
A
10
NC/144M
Q17
Q7
D15
D6
Q14
D13
V
REF
Q4
D3
Q11
Q1
D9
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
NC/288M NC/72M
Document Number: 001-07037 Rev. *C
Page 5 of 30
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