CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
72-Mbit (2M x 36/4M x 18/1M x 72)
Flow-Through SRAM with NoBL™ Architecture
Features
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Functional Description
The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25
are 2.5V, 2M x 36/4M x 18/1M x 72 synchronous flow through
burst SRAMs designed specifically to support unlimited true
back-to-back read or write operations without the insertion of
wait states. The CY7C1471BV25, CY7C1473BV25, and
CY7C1475BV25 are equipped with the advanced No Bus
Latency (NoBL) logic required to enable consecutive read or
write operations with data transferred on every clock cycle. This
feature dramatically improves the throughput of data through the
SRAM, especially in systems that require frequent write-read
transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
Clock Enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133-MHz device).
Write operations are controlled by two or four Byte Write Select
(BW
X
) and a Write Enable (WE) input. All writes are conducted
with on-chip synchronous self timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide easy bank selection
and output tri-state control. To avoid bus contention, the output
drivers are synchronously tri-stated during the data portion of a
write sequence.
For best practice recommendations, refer to the Cypress appli-
cation note
AN1064, SRAM System Guidelines.
No Bus Latency™ (NoBL™) architecture eliminates dead
cycles between write and read cycles
Supports up to 133 MHz bus operations with zero wait states
Data transfers on every clock
Pin compatible and functionally equivalent to ZBT™ devices
Internally self timed output buffer control to eliminate the need
to use OE
Registered inputs for flow through operation
Byte Write capability
2.5V IO supply (V
DDQ
)
Fast clock-to-output times
❐
6.5 ns (for 133-MHz device)
Clock Enable (CEN) pin to enable clock and suspend operation
Synchronous self timed writes
Asynchronous Output Enable (OE)
CY7C1471BV25, CY7C1473BV25 available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and
non-Pb-free 165-ball FBGA package. CY7C1475BV25
available in Pb-free and non-Pb-free 209-ball FBGA package.
Three Chip Enables (CE
1
, CE
2
, CE
3
) for simple depth
expansion.
Automatic power down feature available using ZZ mode or CE
deselect.
IEEE 1149.1 JTAG Boundary Scan compatible
Burst Capability - linear or interleaved burst order
Low standby power
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Selection Guide
Description
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
133 MHz
6.5
305
120
100 MHz
8.5
275
120
Unit
ns
mA
mA
Cypress Semiconductor Corporation
Document #: 001-15013 Rev. *E
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised February 29, 2008
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CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Logic Block Diagram – CY7C1471BV25 (2M x 36)
A0, A1, A
MODE
CLK
CEN
C
CE
ADV/LD
C
WRITE ADDRESS
REGISTER
ADDRESS
REGISTER
A1
D1
A0
D0
BURST
LOGIC
Q1 A1'
A0'
Q0
ADV/LD
BW
A
BW
B
BW
C
BW
D
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
E
DQs
DQP
A
DQP
B
DQP
C
DQP
D
OE
CE1
CE2
CE3
ZZ
INPUT
REGISTER
READ LOGIC
E
SLEEP
CONTROL
Logic Block Diagram – CY7C1473BV25 (4M x 18)
A0, A1, A
MODE
CLK
C
EN
C
CE
ADV/LD
C
WRITE ADDRESS
REGISTER
ADDRESS
REGISTER
A1
D1
A0
D0
A1'
Q1
A0'
Q0
BURST
LOGIC
ADV/LD
BW A
BW B
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
E
DQs
DQP
A
DQPB
WE
OE
CE1
CE2
CE3
ZZ
INPUT
E
REGISTER
READ LOGIC
SLEEP
CONTROL
Document #: 001-15013 Rev. *E
Page 2 of 30
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CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Logic Block Diagram – CY7C1475BV25 (1M x 72)
A0, A1, A
ADDRESS
REGISTER 0
MODE
CLK
CEN
C
WRITE ADDRESS
REGISTER 1
ADV/LD
C
A1
A1'
D1
Q1
A0
A0'
D0 BURST Q0
LOGIC
WRITE ADDRESS
REGISTER 2
ADV/LD
BW
a
BW
b
BW
c
BW
d
BW
e
BW
f
BW
g
BW
h
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
E
E
DQ s
DQ Pa
DQ Pb
DQ Pc
DQ Pd
DQ Pe
DQ Pf
DQ Pg
DQ Ph
WE
INPUT
E
REGISTER 1
INPUT
E
REGISTER 0
OE
CE1
CE2
CE3
ZZ
READ LOGIC
Sleep Control
Document #: 001-15013 Rev. *E
Page 3 of 30
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CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Pin Configurations
Figure 1. 100- Pin TQFP Pinout
ADV/LD
BW
D
BW
C
BW
B
BW
A
CE
1
CE
2
CE
3
V
DD
V
SS
CEN
CLK
WE
OE
A
82
A
100
A
99
A
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
A
BYTE C
BYTE D
DQP
C
DQ
C
DQ
C
V
DDQ
V
SS
DQ
C
DQ
C
DQ
C
DQ
C
V
SS
V
DDQ
DQ
C
DQ
C
NC
V
DD
NC
V
SS
DQ
D
DQ
D
V
DDQ
V
SS
DQ
D
DQ
D
DQ
D
DQ
D
V
SS
V
DDQ
DQ
D
DQ
D
DQP
D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
81
A
CY7C1471BV25
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
44
45
46
47
48
49
50
DQP
B
DQ
B
DQ
B
V
DDQ
V
SS
DQ
B
DQ
B
DQ
B
DQ
B
V
SS
V
DDQ
DQ
B
DQ
B
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SS
DQ
A
DQ
A
DQ
A
DQ
A
V
SS
V
DDQ
DQ
A
DQ
A
DQP
A
BYTE B
BYTE A
38
39
40
41
42
A1
A0
V
SS
MODE
V
DD
A
A
A
A
43
A
A
A
NC/144M
A
Document #: 001-15013 Rev. *E
NC/288M
A
A
A
A
A
Page 4 of 30
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CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Pin Configurations
(continued)
Figure 2. 100-Pin TQFP Pinout
ADV/LD
BW
B
BW
A
CE
1
CE
2
CE
3
V
DD
V
SS
CEN
CLK
WE
OE
NC
NC
A
82
100
A
99
A
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
A
83
A
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQ
B
DQ
B
V
SS
V
DDQ
DQ
B
DQ
B
NC
V
DD
NC
V
SS
DQ
B
DQ
B
V
DDQ
V
SS
DQ
B
DQ
B
DQP
B
NC
V
SS
V
DDQ
NC
NC
NC
BYTE B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
81
A
CY7C1473BV25
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
44
45
46
47
48
49
50
A
NC
NC
V
DDQ
V
SS
NC
DQP
A
DQ
A
DQ
A
V
SS
V
DDQ
DQ
A
DQ
A
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SS
DQ
A
DQ
A
NC
NC
V
SS
V
DDQ
NC
NC
NC
BYTE A
38
39
40
41
42
A1
A0
V
SS
MODE
V
DD
A
A
A
A
43
A
A
A
NC/144M
NC/288M
Document #: 001-15013 Rev. *E
A
A
A
A
A
A
Page 5 of 30
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模拟与混合信号
