CY7C1568KV18/CY7C1570KV18
72-Mbit DDR II+ SRAM Two-Word
Burst Architecture (2.5 Cycle Read Latency)
72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
Features
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Configurations
With Read Cycle Latency of 2.5 cycles:
CY7C1568KV18 – 4M × 18
CY7C1570KV18 – 2M × 36
72-Mbit density (4M × 18, 2M × 36)
550 MHz clock for high bandwidth
Two-word burst for reducing address bus frequency
Double data rate (DDR) interfaces (data transferred at
1100 MHz) at 550 MHz
Available in 2.5 clock cycle latency
Two input clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
Data valid pin (QVLD) to indicate valid data on the output
Synchronous internally self-timed writes
DDR II+ operates with 2.5 cycle read latency when DOFF is
asserted HIGH
Operates similar to DDR I device with 1 cycle read latency when
DOFF is asserted LOW
Core V
DD
= 1.8 V ± 0.1 V; I/O V
DDQ
= 1.4 V to V
DD[1]
❐
Supports both 1.5 V and 1.8 V I/O supply
HSTL inputs and variable drive HSTL output buffers
Available in 165-ball fine pitch ball grid array (FBGA) package
(13 × 15 × 1.4 mm)
Offered in both Pb-free and non Pb-free packages
JTAG 1149.1 compatible test access port
Phase-locked loop (PLL) for accurate data placement
Functional Description
The CY7C1568KV18 and CY7C1570KV18 are 1.8 V
synchronous pipelined SRAMs equipped with DDR II+
architecture. The DDR II+ consists of an SRAM core with
advanced synchronous peripheral circuitry. Addresses for read
and write are latched on alternate rising edges of the input (K)
clock. Write data is registered on the rising edges of both K and
K. Read data is driven on the rising edges of K and K. Each
address location is associated with two 18-bit words
(CY7C1568KV18), or 36-bit words (CY7C1570KV18) that burst
sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
For a complete list of related documentation, click
here.
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Selection Guide
Description
Maximum operating frequency
Maximum operating current
× 18
× 36
550 MHz
550
760
970
500 MHz
500
700
890
450 MHz
450
650
820
400 MHz
400
590
750
Unit
MHz
mA
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V
DDQ
= 1.4 V to V
DD
.
Cypress Semiconductor Corporation
Document Number: 001-15880 Rev. *R
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 11, 2016
CY7C1568KV18/CY7C1570KV18
Logic Block Diagram – CY7C1568KV18
A
(20:0)
LD
K
K
DOFF
21
Write Add. Decode
Read Add. Decode
Address
Register
Write
Reg
2M x 18 Array
Write
Reg
18
2M x 18 Array
CLK
Gen.
Output
Logic
Control
R/W
Read Data Reg.
36
Control
Logic
CQ
CQ
18
V
REF
R/W
BWS
[1:0]
18
18
Reg.
Reg.
Reg. 18
18
DQ
[17:0]
QVLD
Logic Block Diagram – CY7C1570KV18
A
(19:0)
LD
K
K
DOFF
20
Write Add. Decode
Read Add. Decode
Address
Register
Write
Reg
1M x 36 Array
Write
Reg
36
1M x 36 Array
CLK
Gen.
Output
Logic
Control
R/W
Read Data Reg.
72
Control
Logic
CQ
CQ
36
V
REF
R/W
BWS
[3:0]
36
36
Reg.
Reg.
Reg. 36
36
DQ
[35:0]
QVLD
Document Number: 001-15880 Rev. *R
Page 2 of 29
CY7C1568KV18/CY7C1570KV18
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Read Operations ......................................................... 6
Write Operations ......................................................... 6
Byte Write Operations ................................................. 6
DDR Operation ............................................................ 6
Depth Expansion ......................................................... 7
Programmable Impedance .......................................... 7
Echo Clocks ................................................................ 7
Valid Data Indicator (QVLD) ........................................ 7
PLL .............................................................................. 7
Application Example ........................................................ 7
Truth Table ........................................................................ 8
Write Cycle Descriptions ................................................. 8
Write Cycle Descriptions ................................................. 9
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 10
Disabling the JTAG Feature ...................................... 10
Test Access Port ....................................................... 10
Performing a TAP Reset ........................................... 10
TAP Registers ........................................................... 10
TAP Instruction Set ................................................... 10
TAP Controller State Diagram ....................................... 12
TAP Controller Block Diagram ...................................... 13
TAP Electrical Characteristics ...................................... 13
TAP AC Switching Characteristics ............................... 14
TAP Timing and Test Conditions .................................. 15
Identification Register Definitions ................................ 16
Scan Register Sizes ....................................................... 16
Instruction Codes ........................................................... 16
Boundary Scan Order .................................................... 17
Power Up Sequence in DDR II+ SRAM ......................... 18
Power Up Sequence ................................................. 18
PLL Constraints ......................................................... 18
Maximum Ratings ........................................................... 19
Operating Range ............................................................. 19
Neutron Soft Error Immunity ......................................... 19
Electrical Characteristics ............................................... 19
DC Electrical Characteristics ..................................... 19
AC Electrical Characteristics ..................................... 21
Capacitance .................................................................... 21
Thermal Resistance ........................................................ 21
AC Test Loads and Waveforms ..................................... 21
Switching Characteristics .............................................. 22
Switching Waveforms .................................................... 23
Read/Write/Deselect Sequence ................................ 23
Ordering Information ...................................................... 24
Ordering Code Definitions ......................................... 24
Package Diagram ............................................................ 25
Acronyms ........................................................................ 26
Document Conventions ................................................. 26
Units of Measure ....................................................... 26
Document History Page ................................................. 27
Sales, Solutions, and Legal Information ...................... 29
Worldwide Sales and Design Support ....................... 29
Products .................................................................... 29
PSoC® Solutions ...................................................... 29
Cypress Developer Community ................................. 29
Technical Support ..................................................... 29
Document Number: 001-15880 Rev. *R
Page 3 of 29
CY7C1568KV18/CY7C1570KV18
Pin Configurations
The pin configurations for CY7C1568KV18 and CY7C1570KV18 follow.
[2]
Figure 1. 165-ball FBGA (13 × 15 × 1.4 mm) pinout
CY7C1568KV18 (4M × 18)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
A
DQ9
NC
NC
NC
DQ12
NC
V
REF
NC
NC
DQ15
NC
NC
NC
TCK
3
A
NC
NC
DQ10
DQ11
NC
DQ13
V
DDQ
NC
DQ14
NC
NC
DQ16
DQ17
A
4
R/W
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
1
NC/288M
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
QVLD
NC
7
NC/144M
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
LD
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
A
NC
DQ7
NC
NC
NC
NC
V
REF
DQ4
NC
NC
DQ1
NC
NC
TMS
11
CQ
DQ8
NC
NC
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
NC
DQ0
TDI
CY7C1570KV18 (2M × 36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/144M
DQ27
NC
DQ29
NC
DQ30
DQ31
V
REF
NC
NC
DQ33
NC
DQ35
NC
TCK
3
A
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
V
DDQ
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
A
4
R/W
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
2
BWS
3
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
QVLD
NC
7
BWS
1
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
LD
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
A
NC
DQ17
NC
DQ15
NC
NC
V
REF
DQ13
DQ12
NC
DQ11
NC
DQ9
TMS
11
CQ
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
Note
2. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-15880 Rev. *R
Page 4 of 29
CY7C1568KV18/CY7C1570KV18
Pin Definitions
Pin Name
DQ
[x:0]
I/O
Pin Description
Input Output-
Data input output signals.
Inputs are sampled on the rising edge of K and K clocks during valid write
Synchronous operations. These pins drive out the requested data when the read operation is active. Valid data is
driven out on the rising edge of both the K and K clocks during read operations. When read access is
deselected, Q
[x:0]
are automatically tristated.
CY7C1568KV18
DQ
[17:0]
CY7C1570KV18
DQ
[35:0]
Input-
Synchronous load.
Sampled on the rising edge of the K clock. This input is brought LOW when a bus
Synchronous cycle sequence is defined. This definition includes address and read/write direction. All transactions
operate on a burst of 2 data. LD must meet the setup and hold times around edge of K.
Input-
Byte Write Select 0, 1, 2, and 3
Active LOW.
Sampled on the rising edge of the K and K clocks during
Synchronous write operations. Used to select which byte is written into the device during the current portion of the
write operations. Bytes not written remain unaltered.
CY7C1568KV18 BWS
0
controls D
[8:0]
and BWS
1
controls D
[17:9].
CY7C1570KV18
BWS
0
controls D
[8:0]
, BWS
1
controls D
[17:9]
, BWS
2
controls D
[26:18]
and BWS
3
controls D
[35:27]
.
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
Input-
Address inputs.
Sampled on the rising edge of the K clock during active read and write operations.
Synchronous These address inputs are multiplexed for both read and write operations. Internally, the device is
organized as 4M × 18 (2 arrays each of 2M × 18) for CY7C1568KV18, and 2M × 36 (2 arrays each of
1M × 36) for CY7C1570KV18.
Input-
Synchronous read or write input.
When LD is LOW, this input designates the access type (read when
Synchronous R/W is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold times
around edge of K.
Valid output
Valid output indicator.
The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ.
indicator
Input Clock
Input Clock
Echo Clock
Echo Clock
Input
Positive input clock input.
The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q
[x:0]
. All accesses are initiated on the rising edge of K.
Negative input clock input.
K is used to capture synchronous data being presented to the device and
to drive out data through Q
[x:0]
.
Synchronous echo clock outputs.
This is a free running clock and is synchronized to the input clock
(K) of the DDR II+. The timing for the echo clocks is shown in the
Switching Characteristics on page 22.
Synchronous echo clock outputs.
This is a free running clock and is synchronized to the input clock
(K) of the DDR II+. The timing for the echo clocks is shown in the
Switching Characteristics on page 22.
Output impedance matching input.
This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q
[x:0]
output impedance are set to 0.2 × RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, this pin can be connected directly to V
DDQ
, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left
unconnected.
PLL Turn Off
Active LOW.
Connecting this pin to ground turns off the PLL inside the device. The
timing in the PLL turned off operation differs from those listed in this data sheet. For normal operation,
this pin can be connected to a pull up through a 10 k or less pull up resistor. The device behaves in
DDR I mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up
to 167 MHz with DDR I timing.
LD
BWS
0
,
BWS
1
,
BWS
2
,
BWS
3
A
R/W
QVLD
K
K
CQ
CQ
ZQ
DOFF
Input
Document Number: 001-15880 Rev. *R
Page 5 of 29
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