ADVANCE
INFORMATION
CY7C1610KV18, CY7C1625KV18
CY7C1612KV18, CY7C1614KV18
144-Mbit QDR™-II SRAM 2-Word
Burst Architecture
Features
■
Configurations
CY7C1610KV18 – 16M x 8
CY7C1625KV18 – 16M x 9
CY7C1612KV18 – 8M x 18
CY7C1614KV18 – 4M x 36
Separate independent read and write data ports
❐
Supports concurrent transactions
333 MHz clock for high bandwidth
2-word burst on all accesses
Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 666 MHz) at 333 MHz
Two input clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
Single multiplexed address input bus latches address inputs
for read and write ports
Separate port selects for depth expansion
Synchronous internally self timed writes
QDR™-II operates with 1.5 cycle read latency when DOFF is
asserted HIGH
Operates similar to QDR I device with 1 cycle read latency when
DOFF is asserted LOW
Available in ×8, x9, x18, and x36 configurations
Full data coherency providing most current data
Core VDD = 1.8V(±0.1V); IO VDDQ = 1.4V to VDD
Available in 165-ball FBGA package (15 x 17 x 1.4 mm)
Offered in both Pb-free and non Pb-free packages
Variable drive HSTL output buffers
JTAG 1149.1 compatible test access port
Phase Locked Loop (PLL) for accurate data placement
■
■
■
■
Functional Description
The CY7C1610KV18, CY7C1625KV18, CY7C1612KV18, and
CY7C1614KV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR-II architecture. QDR-II architecture consists
of two separate ports to access the memory array. The read port
has dedicated data outputs to support read operations and the
write port has dedicated data inputs to support write operations.
QDR-II architecture has separate data inputs and data outputs
to completely eliminate the need to turn around the data bus that
exists with common IO devices. Each port is accessed through
a common address bus. The read address is latched on the
rising edge of the K clock and the write address is latched on the
rising edge of the K clock. Accesses to the QDR-II read and write
ports are completely independent of one another. To maximize
data throughput, both read and write ports are equipped with
DDR interfaces. Each address location is associated with two
8-bit words (CY7C1610KV18), 9-bit words (CY7C1625KV18),
18-bit
words
(CY7C1612KV18),
or
36-bit
words
(CY7C1614KV18) that burst sequentially into or out of the
device. Because data is transferred into and out of the device on
every rising edge of input clocks (K and K and C and C), memory
bandwidth is maximized while simplifying system design by
eliminating bus turn arounds.
Port selects for each port enable depth expansion. Port selects
allow each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Selection Guide
Parameter
Maximum Operating Frequency
Maximum Operating Current
x8/x9
x18
x36
333 MHz
333
850
870
1060
300 MHz
300
780
810
980
250 MHz
250
680
700
850
200 MHz
200
580
590
710
Unit
MHz
mA
Cypress Semiconductor Corporation
Document #: 001-16238 Rev. **
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 21, 2007
ADVANCE
INFORMATION
CY7C1610KV18, CY7C1625KV18
CY7C1612KV18, CY7C1614KV18
Overview
Figure 1. Logic Block Diagram (CY7C1610KV18)
Block Diagram
D
[7:0]
8
Write
Reg
Write Add. Decode
A
(22:0)
23
Read Add. Decode
Address
Register
Write
Reg
8M x 8 Array
Address
Register
23
A
(22:0)
8M x 8 Array
K
K
CLK
Gen.
Control
Logic
RPS
C
C
DOFF
Read Data Reg.
16
Control
Logic
8
8
Reg.
Reg.
8
Reg.
8
CQ
CQ
V
REF
WPS
NWS
[1:0]
8 Q
[7:0]
Figure 2. Logic Block Diagram (CY7C1625KV18)
Block Diagram
D
[8:0]
9
Write
Reg
Write Add. Decode
A
(22:0)
23
Read Add. Decode
Address
Register
Write
Reg
8M x 9 Array
Address
Register
23
A
(22:0)
8M x 9 Array
K
K
CLK
Gen.
Control
Logic
RPS
C
C
DOFF
Read Data Reg.
18
Control
Logic
9
9
Reg.
Reg.
9
Reg.
9
CQ
CQ
V
REF
WPS
BWS
[0]
9 Q
[8:0]
Document #: 001-16238 Rev. **
Page 2 of 8
ADVANCE
INFORMATION
CY7C1610KV18, CY7C1625KV18
CY7C1612KV18, CY7C1614KV18
Figure 3. Logic Block Diagram (CY7C1612KV18)
Block Diagram
D
[17:0]
18
Write
Reg
Write Add. Decode
A
(21:0)
22
Read Add. Decode
Address
Register
Write
Reg
4M x 18 Array
Address
Register
22
A
(21:0)
4M x 18 Array
K
K
CLK
Gen.
Control
Logic
RPS
C
C
DOFF
Read Data Reg.
36
Control
Logic
18
18
Reg.
Reg.
18
Reg.
CQ
CQ
V
REF
WPS
BWS
[1:0]
18
18
Q
[17:0]
Figure 4. Logic Block Diagram (CY7C1614KV18)
Block Diagram
D
[35:0]
36
Write
Reg
Write Add. Decode
A
(20:0)
21
Read Add. Decode
Address
Register
Write
Reg
2M x 36 Array
Address
Register
21
A
(20:0)
2M x 36 Array
K
K
CLK
Gen.
Control
Logic
RPS
C
C
DOFF
Read Data Reg.
72
Control
Logic
36
36
Reg.
Reg.
36
Reg.
CQ
CQ
V
REF
WPS
BWS
[3:0]
36
36
Q
[35:0]
Document #: 001-16238 Rev. **
Page 3 of 8
ADVANCE
INFORMATION
CY7C1610KV18, CY7C1625KV18
CY7C1612KV18, CY7C1614KV18
Pin Configurations
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
Table 1. CY7C1610KV18 (16M x 8)
[1]
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
A
NC
NC
D4
NC
NC
D5
V
REF
NC
NC
Q6
NC
D7
NC
TCK
3
A
NC
NC
NC
Q4
NC
Q5
V
DDQ
NC
NC
D6
NC
NC
Q7
A
4
WPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
NWS
1
NC/288M
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
A
NWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
RPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
A
NC
NC
NC
D2
NC
NC
V
REF
Q1
NC
NC
NC
NC
NC
TMS
11
CQ
Q3
D3
NC
Q2
NC
NC
ZQ
D1
NC
Q0
D0
NC
NC
TDI
Table 2. CY7C1625KV18 (16M x 9)
[1]
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
A
NC
NC
D5
NC
NC
D6
V
REF
NC
NC
Q7
NC
D8
NC
TCK
3
A
NC
NC
NC
Q5
NC
Q6
V
DDQ
NC
NC
D7
NC
NC
Q8
A
4
WPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
NC
NC/288M
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
A
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
RPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
A
NC
NC
NC
D3
NC
NC
V
REF
Q2
NC
NC
NC
NC
D0
TMS
11
CQ
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
Note
1. NC/288M is not connected to the die and can be tied to any voltage level.
Document #: 001-16238 Rev. **
Page 4 of 8
ADVANCE
INFORMATION
CY7C1610KV18, CY7C1625KV18
CY7C1612KV18, CY7C1614KV18
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
Table 3. CY7C1612KV18 (8M x 18)
[1]
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
A
Q9
NC
D11
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
3
A
D9
D10
Q10
Q11
D12
Q13
V
DDQ
D14
Q14
D15
D16
Q16
Q17
A
4
WPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
1
NC
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
NC/288M
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
RPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
A
NC
Q7
NC
D6
NC
NC
V
REF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Table 4. CY7C1614KV18 (4M x 36)
[1]
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
Q27
D27
D28
Q29
Q30
D30
DOFF
D31
Q32
Q33
D33
D34
Q35
TDO
2
NC/288M
Q18
Q28
D20
D29
Q21
D22
V
REF
Q31
D32
Q24
Q34
D26
D35
TCK
3
A
D18
D19
Q19
Q20
D21
Q22
V
DDQ
D23
Q23
D24
D25
Q25
Q26
A
4
WPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
2
BWS
3
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
BWS
1
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
RPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
D17
D16
Q16
Q15
D14
Q13
VDDQ
D12
Q12
D11
D10
Q10
Q9
A
10
A
Q17
Q7
D15
D6
Q14
D13
V
REF
Q4
D3
Q11
Q1
D9
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Document #: 001-16238 Rev. **
Page 5 of 8
RF/无线
