provided by an active LOW Chip Enable (CE) and active LOW
Output Enable (OE) and three-state drivers. This device has
an automatic power-down feature, reducing the power con-
sumption by 81% when deselected. The CY7C199 is in the
standard 300-mil-wide DIP, SOJ, and LCC packages.
An active LOW Write Enable signal (WE) controls the writ-
ing/reading operation of the memory. When CE and WE inputs
are both LOW, data on the eight data input/output pins (I/O
0
through I/O
7
) is written into the memory location addressed by
the address present on the address pins (A
0
through A
14
).
Reading the device is accomplished by selecting the device
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the con-
tents of the location addressed by the information on address
pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. A die coat is used to improve alpha immunity.
Functional Description
The CY7C199 is a high-performance CMOS static RAM orga-
nized as 32,768 words by 8 bits. Easy memory expansion is
Logic Block Diagram
Pin Configurations
DIP / SOJ / SOIC
Top View
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
22
23
24
25
26
27
28
1
2
3
4
5
6
7
LCC
Top View
3 2 1 28 27
4
26 A
4
5
25 A
3
6
24 A
2
7
23 A
1
8
22 OE
9
21 A
0
20 CE
10
11
19 I/O
7
12
18 I/O
6
1314151617
C199–3
I/O2
GND
I/O3
I/O4
I/O5
A7
A6
A5
VCC
WE
A
8
A
9
A
10
A
11
A
12
A
13
A
14
I/O
0
I/O
1
C199–2
I/O
0
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
CE
WE
OE
I/O
1
ROW DECODER
I/O
2
SENSE AMPS
1024 x 32 x 8
ARRAY
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
A
4
A
3
A
2
A
1
OE
A
0
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
3
I/O
4
I/O
5
OE
A
1
A
2
A
3
A
4
WE
V
CC
A
5
A
6
A
7
A
8
A
9
A
10
A
11
COLUMN
DECODER
POWER
DOWN
I/O
6
I/O
7
TSOP I
Top View
(not to scale)
A
10
A
12
A
13
A
11
A
14
C199–1
21
20
19
18
17
16
15
14
13
12
11
10
9
8
A
0
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
14
A
13
A
12
C199–4
Selection Guide
Maximum Access Time (ns)
Maximum Operating
Current (mA)
L
Maximum CMOS
Standby Current (mA) L
7C199-8
8
120
0.5
7C199-10 7C199-12
10
12
110
160
90
90
0.5
10
0.05
0.05
7C199-15 7C199-20
15
20
155
150
90
90
10
10
0.05
0.05
7C199-25 7C199-35
25
35
150
140
80
70
10
10
0.05
0.05
7C199-45
45
140
10
Shaded area contains advance information.
Cypress Semiconductor Corporation
Document #: 38-05160 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised September 7, 2001
CY7C199
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) ........................................... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
[1]
................................... –0.5V to V
CC
+ 0.5V
DC Input Voltage
[1]
................................ –0.5V to V
CC
+ 0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Military
Ambient Temperature
[2]
0
°
C to +70
°
C
–40
°
C to +85
°
C
–55
°
C to +125
°
C
V
CC
5V
±
10%
5V
±
10%
5V
±
10%
Electrical Characteristics
Over the Operating Range
[3]
7C199-8
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
Input LOW
Voltage
Input Load
Current
Output Leakage
Current
V
CC
Operating
Supply Current
GND < V
I
< V
CC
GND < V
O
< V
CC
,
Output Disabled
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Com’l
L
Mil
5
5
5
0.5
0.05
0.5
0.05
30
5
10
0.05
Test Conditions
V
CC
= Min., I
OH
=–4.0 mA
V
CC
= Min., I
OL
=8.0 mA
2.2
–0.5
–5
–5
Min.
2.4
0.4
V
CC
+0.3V
0.8
+5
+5
120
2.2
–0.5
–5
–5
Max.
7C199-10
Min.
2.4
0.4
V
CC
+0.3V
0.8
+5
+5
110
85
2.2
–0.5
–5
–5
Max.
7C199-12
Min.
2.4
0.4
V
CC
+0.3V
0.8
+5
+5
160
85
2.2
–0.5
–5
–5
Max.
7C199-15
Min.
2.4
0.4
V
CC
+0.3V
0.8
+5
+5
155
100
180
30
5
10
0.05
15
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
I
SB1
Automatic CE
Power-Down
Current— TTL
Inputs
Automatic CE
Power-Down
Current— CMOS
Inputs
Com’l
Max. V
CC
,
CE > V
IH
,
L
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Com’l
Max. V
CC
,
CE > V
CC
– 0.3V L
V
IN
> V
CC
– 0.3V
or V
IN
< 0.3V, f = 0 Mil
I
SB2
Shaded area contains advance information.
Notes:
1. V
IL
(min.) = –2.0V for pulse durations of less than 20 ns.
2. T
A
is the “instant on” case temperature.
3. See the last page of this specification for Group A subgroup testing information.
Document #: 38-05160 Rev. **
Page 2 of 16
CY7C199
Electrical Characteristics
Over the Operating Range
[3]
(continued)
7C199-20
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
Input LOW
Voltage
Input Load
Current
Output Leakage
Current
V
CC
Operating
Supply Current
GND < V
I
< V
CC
GND < V
I
< V
CC
,
Output Disabled
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Com’l
L
Mil
Test Conditions
V
CC
= Min., I
OH
=–4.0 mA
V
CC
= Min., I
OL
=8.0 mA
2.2
–0.5
–5
–5
Min.
2.4
0.4
V
CC
+0.3V
0.8
+5
+5
150
90
170
30
5
10
0.05
15
2.2
-0.5
–5
–5
Max.
7C199-25
Min.
2.4
0.4
V
CC
+0.3V
0.8
+5
+5
150
80
150
30
5
10
0.05
15
2.2
-0.5
–5
–5
Max.
7C199-35
Min.
2.4
0.4
V
CC
+0.3V
0.8
+5
+5
140
70
150
25
5
10
0.05
15
2.2
-0.5
–5
–5
Max.
7C199-45
Min.
2.4
0.4
V
CC
+0.3V
0.8
+5
+5
140
70
150
25
5
10
0.05
15
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
mA
mA
mA
µA
mA
I
SB1
Automatic CE
Power-Down
Current—
TTL Inputs
Automatic CE
Power-Down
Current—
CMOS Inputs
Max. V
CC
, CE > V
IH
, Com’l
V
IN
> V
IH
L
or V
IN
< V
IL
, f = f
MAX
Com’l
Max. V
CC
,
CE > V
CC
– 0.3V
L
V
IN
> V
CC
– 0.3V or
V
IN
< 0.3V, f=0
Mil
I
SB2
]
Capacitance
[4]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
8
8
Unit
pF
pF
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05160 Rev. **
Page 3 of 16
CY7C199
AC Test Loads and Waveforms
[5]
R1 481
Ω
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R2
255
Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
R2
255
Ω
3.0V
10%
GND
R1 481
Ω
ALL INPUT PULSES
90%
90%
10%
≤
t
r
≤
t
r
C199–6
C199–5
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT
167
Ω
1.73V
OUTPUT
Data Retention Characteristics
Over the Operating Range (L version only)
Parameter
V
DR
I
CCDR
t
CDR[4]
t
R [5]
Description
V
CC
for Data Retention
Data Retention Current
V
CC
= V
DR
= 2.0V,
CE > V
CC
– 0.3V,
Com’l L
V
IN
> V
CC
– 0.3V or
Chip Deselect to Data Retention Time V
IN
< 0.3V
Operation Recovery Time
Com’l
Conditions
[6]
Min.
2.0
Max.
Unit
V
µA
10
0
200
µA
ns
µs
Data Retention Waveform
DATA RETENTION MODE
V
CC
3.0V
t
CDR
CE
C199–7
V
DR
> 2V
3.0V
t
R
Note:
5. t
R
< 3 ns for the -12 and the -15 speeds. t
R
< 5 ns for the -20 and slower speeds
6. No input may exceed V
CC
+ 0.5V.
Document #: 38-05160 Rev. **
Page 4 of 16
CY7C199
Switching Characteristics
Over the Operating Range
[3, 7]
7C199-8
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[8]
OE HIGH to High Z
[8, 9]
CE LOW to Low Z
[8]
CE HIGH to High Z
[8,9]
CE LOW to Power-Up
CE HIGH to Power-Down
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z
[9]
WE HIGH to Low Z
[8]
3
8
7
7
0
0
7
5
0
5
3
0
8
10
7
7
0
0
7
5
0
6
3
3
4
0
10
12
9
9
0
0
8
8
0
7
3
0
5
3
5
0
12
15
10
10
0
0
9
9
0
7
3
8
4.5
0
5
3
5
0
15
8
8
3
10
5
0
5
3
7
10
10
3
12
5
0
7
12
12
3
15
7
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
7C199-10
Min.
Max.
7C199-12
Min.
Max.
7C199-15
Min.
Max.
Unit
WRITE CYCLE
[10, 11]
Shaded area contains advance information.
Notes:
7. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels of 1.5V,
input pulse levels of 0 to 3.0V, and output loading of the specified I
OL
/I
OH
and 30-pF load capacitance.
8. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
9. t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
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