CY8C24123A
CY8C24223A
CY8C24423A
PSoC
®
Programmable System-on-Chip
PSoC
®
Programmable System-on-Chip
Features
■
■
Powerful Harvard-architecture processor
❐
M8C processor speeds up to 24 MHz
❐
8 × 8 multiply, 32-bit accumulate
❐
Low power at high speed
❐
Operating voltage: 2.4 V to 5.25 V
❐
Operating voltages down to 1.0 V using on-chip switch mode
pump (SMP)
❐
Industrial temperature range: –40 °C to +85 °C
Advanced peripherals (PSoC
®
blocks)
❐
Six rail-to-rail analog PSoC blocks provide:
• Up to 14-bit analog-to-digital converters (ADCs)
• Up to 9-bit digital-to-analog converters (DACs)
• Programmable gain amplifiers (PGAs)
• Programmable filters and comparators
❐
Four digital PSoC blocks provide:
• 8- to 32-bit timers and counters, 8- and 16-bit pulse-width
modulators (PWMs)
• Cyclical redundancy check (CRC) and pseudo random
sequence (PRS) modules
• Full-duplex universal asynchronous receiver transmitter
(UART)
• Multiple serial peripheral interface (SPI) masters or slaves
• Can connect to all general-purpose I/O (GPIO) pins
❐
Complex peripherals by combining blocks
Precision, programmable clocking
❐
Internal ±5% 24- / 48-MHz main oscillator
❐
High accuracy 24 MHz with optional 32 kHz crystal and
phase-locked loop (PLL)
❐
Optional external oscillator up to 24 MHz
❐
Internal oscillator for watchdog and sleep
Flexible on-chip memory
❐
4 KB flash program storage 50,000 erase/write cycles
❐
256-bytes SRAM data storage
❐
In-system serial programming (ISSP)
❐
Partial flash updates
❐
Flexible protection modes
❐
Electronically erasable programmable read only memory
(EEPROM) emulation in flash
Programmable pin configurations
❐
25-mA sink, 10-mA source on all GPIOs
❐
Pull-up, pull-down, high Z, strong, or open-drain drive modes
on all GPIOs
❐
Eight standard analog inputs on all GPIOs, and
four additional analog inputs with restricted routing
❐
Two 30 mA analog outputs on all GPIOs
❐
Configurable interrupt on all GPIOs
New CY8C24x23A PSoC device
❐
Derived from the CY8C24x23 device
❐
Low power and low voltage (2.4 V)
Additional system resources
2
❐
I C slave, master, and multi-master to 400 kHz
❐
Watchdog and sleep timers
❐
User-configurable low-voltage detection (LVD)
❐
Integrated supervisory circuit
❐
On-chip precision voltage reference
Complete development tools
❐
Free development software (PSoC Designer™)
❐
Full-featured, in-circuit emulator (ICE), and programmer
❐
Full-speed emulation
❐
Complex breakpoint structure
❐
128 KB trace memory
■
■
■
Logic Block Diagram
Port 2 Port 1 Port 0
Analog
Drivers
PSoC CORE
System Bus
Global Digital Interconnect
SRAM
256 Bytes
Interrupt
Controller
SROM
Global Analog Interconnect
Flash 4KB
Sleep and
Watchdog
■
CPU Core (M8C)
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
■
DIGITAL SYSTEM
Digital
Block
Array
ANALOG SYSTEM
Analog
Block
Array
Analog
Ref
Analog
Input
Muxing
■
Digital
Clocks
Multiply
Accum.
Decimator
I
2
C
POR and LVD
System Resets
Internal
Voltage
Ref.
Switch
Mode
Pump
SYSTEM RESOURCES
Errata:
For information on silicon errata, see
“Errata”
on page 67. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 38-12028 Rev. *W
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 3, 2017
CY8C24123A
CY8C24223A
CY8C24423A
More Information
Cypress provides a wealth of data at
www.cypress.com
to help you to select the right PSoC device for your design, and to help you
to quickly and effectively integrate the device into your design. Following is an abbreviated list for PSoC 1:
■
■
■
■
Overview:
PSoC Portfolio, PSoC Roadmap
Product Selectors:
PSoC 1, PSoC 3, PSoC 4,
or
PSoC 5LP
In addition,
PSoC Designer
offers a device selection tool within
PSoC 1, at the time of creating a new project.
Datasheets: Describe and provide electrical specifications for
all the PSoC 1 family of devices. Visit the
PSoC 1 datasheets
web page for a complete list
Application notes and code examples:
❐
Visit the
PSoC 1 Code Examples
web page for a comprehen-
sive list of code examples
❐
Cypress offers a large number of PSoC application notes
covering a broad range of topics, from basic to advanced
level. Recommended application notes for getting started
with PSoC 1 are:
•
AN75320:
Getting Started with PSoC® 1
•
AN2094:
PSoC
®
1 - Getting Started with GPIO
•
AN2015:
PSoC
®
1 - Getting Started with Flash & E2PROM
•
AN2014:
Basics of PSoC
®
1 Programming
•
AN32200:
PSoC
®
1 - Clocks and Global Resources
•
AN2010:
PSoC
®
1 Best Practices and Recommendations
Technical Reference Manual (TRM):
❐
Visit the
PSoC 1 TRM
page for the complete list of TRMs.
Following documents provide detailed descriptions of the Ar-
chitecture, Programming specification and Register map de-
tails of CY8C2XXXX PSoC 1 device family.
• PSoC1 CY8C2XXXX TRM
•
PSoC1 ISSP Programming Specifications
■
Development Kits:
❐
CY3210 - CY8C24x23 PSoC(R) Evaluation Pods (EvalPod)
are 28-pin PDIP adapters that seamlessly connect any PSoC
device to the 28-pin PDIP connector on any Cypress PSoC
development kit. CY3210-24x23 provides evaluation of the
CY8C24x23A PSoC device family on any PSoC developer
kit. PSoC developer kits are sold separately.
❐
Visit the
PSoC® 1 Kits
page and refer the
Kit Selector Guide
document to find out the suitable development kits and
debuggers for all PSoC 1 families.
The
CY3217-MiniProg1
and
CY8CKIT-002 PSoC® MiniProg3
device provide an interface for flash programming.
Knowledge Base Articles (KBA):
Provide design and appli-
cation tips from experts on the devices/kits. For example,
Flash
read/write access from firmware,
explains how we can read
and write to flash in PSoC 1 devices
■
■
■
PSoC Designer
PSoC Designer
is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design
of systems based on CapSense (see
Figure 1).
With PSoC Designer, you can:
1. Drag and drop user modules to build your hardware system
3. Configure user module
design in the main design workspace
4. Explore the library of user modules
2. Codesign your application firmware with the PSoC hardware,
5. Review user module datasheets
using the PSoC Designer IDE C compiler
Figure 1. PSoC Designer Features
1
3
5
Document Number: 38-12028 Rev. *W
2
4
Page 2 of 71
CY8C24123A
CY8C24223A
CY8C24423A
Contents
PSoC Functional Overview .............................................. 4
PSoC Core .................................................................. 4
Digital System ............................................................. 4
Analog System ............................................................ 5
Additional System Resources ..................................... 6
PSoC Device Characteristics ...................................... 6
Getting Started .................................................................. 7
Application Notes ........................................................ 7
Development Kits ........................................................ 7
Training ....................................................................... 7
CYPros Consultants .................................................... 7
Solutions Library .......................................................... 7
Technical Support ....................................................... 7
Development Tools .......................................................... 8
PSoC Designer Software Subsystems ........................ 8
Designing with PSoC Designer ....................................... 9
Select User Modules ................................................... 9
Configure User Modules .............................................. 9
Organize and Connect ................................................ 9
Generate, Verify, and Debug ....................................... 9
Pinouts ............................................................................ 10
8-Pin Part Pinout ....................................................... 10
20-Pin Part Pinout ..................................................... 11
28-Pin Part Pinout ..................................................... 12
32-Pin Part Pinout ..................................................... 13
56-Pin Part Pinout ..................................................... 14
Register Reference ......................................................... 15
Register Conventions ................................................ 15
Register Mapping Tables .......................................... 15
Electrical Specifications ................................................ 18
Absolute Maximum Ratings ....................................... 18
Operating Temperature ............................................. 19
DC Electrical Characteristics ..................................... 19
AC Electrical Characteristics ..................................... 37
Packaging Information ................................................... 51
Packaging Dimensions .............................................. 51
Thermal Impedances ................................................. 57
Capacitance on Crystal Pins ..................................... 57
Solder Reflow Specifications ..................................... 57
Development Tool Selection ......................................... 58
Software .................................................................... 58
Development Kits ...................................................... 58
Evaluation Tools ........................................................ 58
Device Programmers ................................................. 59
Accessories (Emulation and Programming) .............. 59
Ordering Information ...................................................... 60
Ordering Code Definitions ......................................... 60
Acronyms ........................................................................ 61
Acronyms Used ......................................................... 61
Reference Documents .................................................... 61
Document Conventions ................................................. 62
Units of Measure ....................................................... 62
Numeric Conventions ................................................ 62
Glossary .......................................................................... 62
Errata ............................................................................... 67
Part Numbers Affected .............................................. 67
CY8C24123A Qualification Status ............................ 67
CY8C24123A Errata Summary ................................. 67
Document History Page ................................................. 68
Sales, Solutions, and Legal Information ...................... 71
Worldwide Sales and Design Support ....................... 71
Products .................................................................... 71
PSoC® Solutions ...................................................... 71
Cypress Developer Community ................................. 71
Technical Support ..................................................... 71
Document Number: 38-12028 Rev. *W
Page 3 of 71
CY8C24123A
CY8C24223A
CY8C24423A
PSoC Functional Overview
The PSoC family consists of many programmable
system-on-chips with on-chip controller devices. These devices
are designed to replace multiple traditional MCU-based system
components with a low-cost single-chip programmable device.
PSoC devices include configurable blocks of analog and digital
logic, and programmable interconnects. This architecture makes
it possible for you to create customized peripheral configurations
that match the requirements of each individual application.
Additionally, a fast CPU, flash program memory, SRAM data
memory, and configurable I/O are included in a range of
convenient pinouts and packages.
The PSoC architecture, shown in
Figure 2,
consists of four main
areas: PSoC core, digital system, analog system, and system
resources. Configurable global busing allows combining all the
device resources into a complete custom system. The PSoC
CY8C24x23A family can have up to three I/O ports that connect
to the global digital and analog interconnects, providing access
to four digital blocks and six analog blocks.
Digital System
The digital system consists of four digital PSoC blocks. Each
block is an 8-bit resource that may be used alone or combined
with other blocks to form 8-, 16-, 24-, and 32-bit peripherals,
which are called user module references.
Figure 2. Digital System Block Diagram
Port 1
Port 2
Port 0
Digital Clocks
From Core
To System Bus
To Analog
System
DIGITAL SYSTEM
Digital PSoC Block Array
Row Input
Configuration
8
8
Row 0
DBB00
DBB01
DCB02
4
DCB03
4
8
8
Row Output
Configuration
PSoC Core
The PSoC core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPIOs.
The M8C CPU core is a powerful processor with speeds up to
24 Hz, providing a four-MIPS 8-bit Harvard-architecture
microprocessor. The CPU uses an interrupt controller with
11 vectors, to simplify programming of real time embedded
events. Program execution is timed and protected using the
included sleep and watchdog timers (WDT).
Memory encompasses 4 KB of flash for program storage,
256 bytes of SRAM for data storage, and up to 2 KB of EEPROM
emulated using the flash. Program flash uses four protection
levels on blocks of 64 bytes, allowing customized software IP
protection.
The PSoC device incorporates flexible internal clock generators,
including a 24 MHz internal main oscillator (IMO) accurate to
±2.5% to ±5% over temperature and voltage
[1]
. The 24 MHz IMO
can also be doubled to 48 MHz for use by the digital system. A
low power 32 kHz internal low speed oscillator (ILO) is provided
for the sleep timer and WDT. If crystal accuracy is required, the
ECO (32.768 kHz external crystal oscillator) is available for use
as a real time clock (RTC) and can optionally generate a
crystal-accurate 24 MHz system clock using a PLL. The clocks,
together with programmable clock dividers (as a System
Resource), provide the flexibility to integrate almost any timing
requirement into the PSoC device.
PSoC GPIOs provide connection to the CPU, digital, and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external
interfacing. Every pin can generate a system interrupt on high
level, low level, and change from last read.
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
Digital peripheral configurations are:
■
■
■
■
■
■
■
■
■
■
PWMs (8- and 16-bit)
PWMs with dead band (8- and 16-bit)
Counters (8- to 32-bit)
Timers (8- to 32-bit)
UART 8-bit with selectable parity
SPI master and slave
I
2
C slave and multi-master (one is available as a system
resource)
CRC generator (8- to 32-bit)
IrDA
PRS generators (8- to 32-bit)
The digital blocks may be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This gives a choice of
system resources for your application. Family resources are
shown in
Table 1 on page 6.
Note
1. Errata:
When the device is operated within 0
°
C to 70
°
C, the frequency tolerance is reduced to
±
2.5%, but if operated at extreme temperature (below 0
°
C or above
70
°
C), frequency tolerance deviates from
±
2.5% to
±
5%. For more information, see
“Errata”
on page 67.
Document Number: 38-12028 Rev. *W
Page 4 of 71
CY8C24123A
CY8C24223A
CY8C24423A
Analog System
The analog system consists of six configurable blocks, each
consisting of an opamp circuit that allows the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common PSoC analog functions (most
available as user modules) are:
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Figure 3. Analog System Block Diagram
P0[7]
P0[5]
P0[3]
P0[1]
AGNDIn RefIn
P0[6]
P0[4]
P0[2]
P0[0]
P2[6]
ADCs (up to two, with 6- to 14-bit resolution, selectable as
incremental, delta sigma, and SAR)
Filters (two and four pole band-pass, low-pass, and notch)
Amplifiers (up to two, with selectable gain to 48x)
Instrumentation amplifiers (one with selectable gain to 93x)
Comparators (up to two, with 16 selectable thresholds)
DACs (up to two, with 6 to 9-bit resolution)
Multiplying DACs (up to two, with 6 to 9-bit resolution)
High current output drivers (two with 30 mA drive as a PSoC
Core resource)
1.3 V reference (as a system resource)
DTMF dialer
Modulators
Correlators
Peak detectors
Many other topologies possible
P2[3]
P2[4]
P2[2]
P2[0]
P2[1]
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
Block Array
ACB00
ASC10
ASD20
ACB01
ASD11
ASC21
Analog blocks are arranged in a column of three, which includes
one continuous time (CT) and two switched capacitor (SC)
blocks, as shown in
Figure 3
Analog Reference
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 38-12028 Rev. *W
Page 5 of 71
模拟与混合信号
