Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
EZ-USB FX3:
SuperSpeed USB Controller
EZ-USB
®
FX3: SuperSpeed USB Controller
CYUSB301X/CYUSB201X
®
Features
■
Universal serial bus (USB) integration
❐
USB 3.1, Gen 1 and USB 2.0 peripherals compliant with USB
3.1 Specification Revision 1.0 (TID # 340800007)
❐
5-Gbps SuperSpeed PHY compliant with USB 3.1 Gen 1
❐
High-speed On-The-Go (HS-OTG) host and peripheral
compliant with OTG Supplement Version 2.0
❐
Thirty-two physical endpoints
General Programmable Interface (GPIF™ II)
❐
Programmable 100-MHz GPIF II enables connectivity to a
wide range of external devices
❐
8-, 16-, 24-, and 32-bit data bus
❐
Up to16 configurable control signals
Fully accessible 32-bit CPU
❐
ARM926EJ core with 200-MHz operation
❐
512-KB or 256-KB embedded SRAM
Additional connectivity to the following peripherals
❐
SPI master at up to 33 MHz
❐
UART support of up to 4 Mbps
2
❐
I C master controller at 1 MHz
2
❐
I S master (transmitter only) at sampling frequencies of
8 kHz, 16 kHz, 32 kHz, 44.1 kHz, 48 kHz, 96 kHz and 192 kHz
Selectable clock input frequencies
❐
19.2, 26, 38.4, and 52 MHz
❐
19.2-MHz crystal input support
Ultra low-power in core power-down mode
❐
Less than 60 µA with VBATT on and 20 µA with VBATT off
Independent power domains for core and I/O
❐
Core operation at 1.2 V
❐
I2S, UART, and SPI operation at 1.8 to 3.3 V
2
❐
I C operation at 1.2 V to 3.3 V
Package options
❐
121-ball, 10- × 10-mm, 0.8-mm pitch Pb-free ball grid array
(BGA)
❐
See
Table 24
for details on the seven FX3 variants
EZ-USB
®
Software Development Kit (SDK) for code devel-
opment of firmware and PC Applications
❐
Includes RTOS Framework (using ThreadX Version 5)
Firmware examples covering all I/O modules
❐
Visual Studio host examples using C++ and C#
❐
■
SuperSpeed Explorer Board available for rapid prototyping
❐
Several accessory boards also available:
• Adapter boards for Xilinx/Altera FPGA development
• Adapter board for Video development
• CPLD board for concept testing and initial development
■
Applications
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Digital video camcorders
Digital still cameras
Printers
Scanners
Video capture cards
Test and measurement equipment
Surveillance cameras
Personal navigation devices
Medical imaging devices
Video IP phones
Portable media players
Industrial cameras
Data loggers
Data acquisition
High-performance Human Interface Devices (gesture
recognition)
■
■
■
■
■
Functional Description
For a complete list of related documentation, click
here.
■
■
Cypress Semiconductor Corporation
Document Number: 001-52136 Rev. *X
•
198 Champion Court
•
San Jose
,
CA 95134-1709
• 408-943-2600
Revised December 17, 2018
CYUSB301X/CYUSB201X
Logic Block Diagram
Document Number: 001-52136 Rev. *X
Page 2 of 58
CYUSB301X/CYUSB201X
More Information
Cypress provides a wealth of data at
www.cypress.com
to help you to select the right <product> device for your design, and to help
you to quickly and effectively integrate the device into your design.
■
■
■
Overview:
USB Portfolio, USB Roadmap
USB 3.0 Product Selectors:
FX3, FX3S, CX3, GX3, HX3
Application notes: Cypress offers a large number of USB appli-
cation notes covering a broad range of topics, from basic to
advanced level. Recommended application notes for getting
started with FX3 are:
❐
AN75705
- Getting Started with EZ-USB FX3
❐
AN76405
- EZ-USB FX3 Boot Options
❐
AN70707
- EZ-USB FX3/FX3S Hardware Design Guidelines
and Schematic Checklist
❐
AN65974
- Designing with the EZ-USB FX3 Slave FIFO In-
terface
❐
AN75779
- How to Implement an Image Sensor Interface with
EZ-USB FX3 in a USB Video Class (UVC) Framework
❐
AN86947
- Optimizing USB 3.0 Throughput with EZ-USB
FX3
❐
AN84868
- Configuring an FPGA over USB Using Cypress
EZ-USB FX3
❐
AN68829
- Slave FIFO Interface for EZ-USB FX3: 5-Bit Ad-
dress Mode
AN73609
- EZ-USB FX2LP/ FX3 Developing Bulk-Loop Ex-
ample on Linux
❐
AN77960
- Introduction to EZ-USB FX3 High-Speed USB
Host Controller
❐
AN76348
- Differences in Implementation of EZ-USB FX2LP
and EZ-USB FX3 Applications
❐
AN89661
- USB RAID 1 Disk Design Using EZ-USB FX3S
❐
■
Code Examples:
❐
USB Hi-Speed
❐
USB Full-Speed
❐
USB SuperSpeed
Technical Reference Manual (TRM):
❐
EZ-USB FX3
Technical Reference Manual
Development Kits:
❐
CYUSB3KIT-003,
EZ-USB FX3 SuperSpeed Explorer Kit
❐
CYUSB3KIT-001,
EZ-USB FX3 Development Kit
Models:
IBIS
■
■
■
EZ-USB FX3 Software Development Kit
Cypress delivers the complete software and firmware stack for FX3, in order to easily integrate SuperSpeed USB into any embedded
application. The
Software Development Kit
(SDK) comes with tools, drivers and application examples, which help accelerate appli-
cation development.
GPIF™ II Designer
The
GPIF II Designer
is a graphical software that allows designers to configure the GPIF II interface of the EZ-USB FX3 USB 3.0
Device Controller.
The tool allows users the ability to select from one of five Cypress supplied interfaces, or choose to create their own GPIF II interface
from scratch. Cypress has supplied industry standard interfaces such as Asynchronous and Synchronous Slave FIFO, Asynchronous
and Synchronous SRAM, and Asynchronous SRAM. Designers who already have one of these pre-defined interfaces in their system
can simply select the interface of choice, choose from a set of standard parameters such as bus width (x8, 16, x32) endianess, clock
settings, and compile the interface. The tool has a streamlined three step GPIF interface development process for users who need a
customized interface. Users are able to first select their pin configuration and standard parameters. Secondly, they can design a virtual
state machine using configurable actions. Finally, users can view output timing to verify that it matches the expected timing. Once the
three step process is complete, the interface can be compiled and integrated with FX3.
Document Number: 001-52136 Rev. *X
Page 3 of 58
CYUSB301X/CYUSB201X
Contents
Functional Overview ..........................................................5
Application Examples ....................................................5
USB Interface ......................................................................6
OTG ...............................................................................6
ReNumeration ...............................................................7
VBUS Overvoltage Protection .......................................7
Carkit UART Mode ........................................................7
GPIF II ..................................................................................8
CPU ......................................................................................8
JTAG Interface ....................................................................8
Other Interfaces ..................................................................8
SPI Interface ..................................................................8
UART Interface ..............................................................9
I2C Interface ..................................................................9
I2S Interface ..................................................................9
Boot Options .......................................................................9
Reset ....................................................................................9
Hard Reset ....................................................................9
Soft Reset ......................................................................9
Clocking ............................................................................10
32-kHz Watchdog Timer Clock Input ...........................10
Power .................................................................................11
Power Modes ..............................................................11
Digital I/Os .........................................................................13
GPIOs .................................................................................13
System-level ESD .............................................................13
Pin Configurations ...........................................................14
Pin Description .................................................................15
Electrical Specifications ..................................................19
Absolute Maximum Ratings .........................................19
Operating Conditions ...................................................19
DC Specifications ........................................................19
Thermal Characteristics ...................................................21
AC Timing Parameters .....................................................21
GPIF II lines AC characteristics at 100 MHz ...............21
GPIF II PCLK Jitter characteristics ..............................21
GPIF II Timing .............................................................22
Slave FIFO Interface ...................................................25
Host Processor Interface (P-Port) Timing ...................31
Serial Peripherals Timing ............................................38
Reset Sequence ..........................................................43
Package Diagram ..............................................................44
Ordering Information ........................................................45
Ordering Code Definitions ...........................................45
Acronyms ..........................................................................46
Document Conventions ...................................................46
Units of Measure .........................................................46
Errata .................................................................................47
Qualification Status .....................................................47
Errata Summary ..........................................................47
Document History Page ...................................................53
Sales, Solutions, and Legal Information ........................58
Worldwide Sales and Design Support .........................58
Products ......................................................................58
PSoC® Solutions ........................................................58
Cypress Developer Community ...................................58
Technical Support .......................................................58
Document Number: 001-52136 Rev. *X
Page 4 of 58
stm32/stm8
