Preliminary Information
AMD Duron
Processor
Data Sheet
TM
Publication #
23802
Rev:
B
Issue Date:
June 2000
Preliminary Information
© 2000 Advanced Micro Devices, Inc.
All rights reserved.
The contents of this document are provided in connection with Advanced
Micro Devices, Inc. (“AMD”) products. AMD makes no representations or
warranties with respect to the accuracy or completeness of the contents of
this publication and reserves the right to make changes to specifications and
product descriptions at any time without notice. No license, whether express,
implied, arising by estoppel or otherwise, to any intellectual property rights
is granted by this publication. Except as set forth in AMD’s Standard Terms
and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims
any express or implied warranty, relating to its products including, but not
limited to, the implied warranty of merchantability, fitness for a particular
purpose, or infringement of any intellectual property right.
AMD’s products are not designed, intended, authorized or warranted for use
as components in systems intended for surgical implant into the body, or in
other applications intended to support or sustain life, or in any other applica-
tion in which the failure of AMD’s product could create a situation where per-
sonal injury, death, or severe property or environmental damage may occur.
AMD reserves the right to discontinue or make changes to its products at any
time without notice.
Trademarks
AMD, the AMD logo, AMD Duron, and combinations thereof, and 3DNow! are trademarks of Advanced Micro
Devices, Inc.
MMX is a trademark of Intel Corporation.
Digital and Alpha are trademarks of Digital Equipment Corporation.
Other product names used in this publication are for identification purposes only and may be trademarks of
their respective companies.
Preliminary Information
23802B—June 2000
AMD Duron™ Processor Data Sheet
Contents
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
1
2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1
2.1
2.2
2.3
2.4
AMD Duron™ Processor Microarchitecture Summary . . . . . 2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Signaling Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Push-Pull (PP) Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
AMD System Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
4
Logic Symbol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1
Power Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Full-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Stop Grant and Sleep States. . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Probe State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Connection and Disconnection Protocol . . . . . . . . . . . . . . . . 11
Connection Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Connection State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2
5
6
Thermal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
Voltage Identification (VID[4:0]) . . . . . . . . . . . . . . . . . . . . . . 20
Frequency Identification (FID[3:0]) . . . . . . . . . . . . . . . . . . . . 20
SYSCLK and SYSCLK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
VCCA AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . . 21
Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SYSCLK and SYSCLK# AC and DC Characteristics . . . . . . 23
AMD System Bus AC/DC Characteristics . . . . . . . . . . . . . . . 24
Push-Pull Mode IV Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
System Bus AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26
Southbridge AC and DC Characteristics . . . . . . . . . . . . . . . . 27
APIC Pin AC and DC Characteristics . . . . . . . . . . . . . . . . . . . 29
Power-Up Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Signal Sequence and Timing Description . . . . . . . . . . . . . . . . 31
Clock Multiplier Selection (FID[3:0]) . . . . . . . . . . . . . . . . . . . 34
Processor Warm Reset Requirements . . . . . . . . . . . . . . . . . . 36
The AMD Duron Processor and Northbridge Reset Pins . . . 36
7
Signal and Power-Up Requirements . . . . . . . . . . . . . . . . . . . . 31
7.1
7.2
Contents
iii
Preliminary Information
AMD Duron™ Processor Data Sheet
23802B—June 2000
8
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
8.1
8.2
8.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Socket Tabs for Heatsink Clips . . . . . . . . . . . . . . . . . . . . . . . 41
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Detailed Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A20M# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AMD Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AMD System Bus Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLKFWDRST Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLKIN, RSTCLK (SYSCLK) Pins . . . . . . . . . . . . . . . . . . . . . .
CONNECT Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COREFB and COREFB# Pins . . . . . . . . . . . . . . . . . . . . . . . . .
DBRDY and DBREQ# Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . .
FERR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FID[3:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FLUSH# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IGNNE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INIT# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INTR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
K7CLKOUT and K7CLKOUT# Pins . . . . . . . . . . . . . . . . . . . .
Key Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NC Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NMI Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PGA Orientation Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Bypass and Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWROK Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SADDIN[1]# and SADDOUT[1:0]# Pins . . . . . . . . . . . . . . . . .
Scan Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCHECK[7:0]# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SMI# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STPCLK# Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SYSCLK and SYSCLK# Pins . . . . . . . . . . . . . . . . . . . . . . . . . .
SYSVREFMODE Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCCA Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VID[4:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VREFSYS Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ZN, VCC_Z, ZP, and VSS_Z Pins . . . . . . . . . . . . . . . . . . . . . . .
43
51
59
59
59
59
59
59
59
59
59
59
60
60
61
61
61
61
61
61
61
62
62
62
62
62
62
63
63
63
63
63
63
63
63
64
64
9
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
9.1
9.2
9.3
10
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Standard AMD Duron Processor Products. . . . . . . . . . . . . . . . . . . . . 67
Appendix A Conventions, Abbreviations, and References . . . . . . . . . . . . . . . . . . . . .69
iv
Contents
Preliminary Information
23802B—June 2000
AMD Duron™ Processor Data Sheet
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Typical AMD Duron™ Processor System Block Diagram . . . . . 3
Logic Symbol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
AMD Duron Processor Power Management States. . . . . . . . . . . 9
Example System Bus Disconnection Sequence . . . . . . . . . . . . . 13
Exiting Stop Grant State/Bus Reconnection Sequence . . . . . . 14
System Connection States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Processor Connection States . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SYSCLK and SYSCLK# Differential Clock Signals . . . . . . . . . 23
PP Mode Pulldown IV Curve. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 10. PP Mode Pullup IV Curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 11. Signal Relationship Requirements during Power-Up
Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 12. Typical SIP Protocol Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 13. PGA Package, Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 14. PGA Package, Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 15. PGA Package, Side View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 16. Socket A with Outline of Socket and Heatsink Tab . . . . . . . . . 41
Figure 17. AMD Duron Processor Pin Diagram—Topside View . . . . . . . . 44
Figure 18. PGA OPN Example for the AMD Duron Processor. . . . . . . . . . 67
List of Figures
v
