DA14580
Bluetooth Low Energy 4.2 SoC
General Description
The DA14580 integrated circuit has a fully integrated
radio transceiver and baseband processor for
Blue-
tooth
®
low energy.
It can be used as a standalone
application processor or as a data pump in hosted sys-
tems.
The DA14580 supports a flexible memory architecture
for storing Bluetooth profiles and custom application
code, which can be updated over the air (OTA). The
qualified
Bluetooth low energy
protocol stack is stored
in a dedicated ROM. All software runs on the ARM
®
Cortex
®
-M0 processor via a simple scheduler.
The
Bluetooth low energy
firmware includes the
L2CAP service layer protocols, Security Manager
(SM), Attribute Protocol (ATT), the Generic Attribute
Profile (GATT) and the Generic Access Profile (GAP).
All profiles published by the Bluetooth SIG as well as
custom profiles are supported.
The transceiver interfaces directly to the antenna and
is fully compliant with the
Bluetooth 4.2
standard.
The DA14580 has dedicated hardware for the Link
Layer implementation of
Bluetooth low energy
and
interface controllers for enhanced connectivity capabili-
ties.
FINAL
Features
Complies with
Bluetooth
V4.2, ETSI EN 300 328 and
EN 300 440 Class 2 (Europe), FCC CFR47 Part 15
(US) and ARIB STD-T66 (Japan)
Processing power
16 MHz 32 bit ARM Cortex-M0 with SWD inter-
face
Dedicated Link Layer Processor
AES-128 bit encryption Processor
Memories
32 kB One-Time-Programmable (OTP) memory
________________________________________________________________________________________________
42 kB System SRAM
84 kB ROM
8 kB Retention SRAM
Power management
Integrated Buck/Boost DC-DC converter
P0, P1, P2 and P3 ports with 3.3 V tolerance
Easy decoupling of only 4 supply pins
Supports coin (typ. 3.0 V) and alkaline (typ. 1.5 V)
battery cells
10-bit ADC for battery voltage measurement
Digital controlled oscillators
16 MHz crystal (±20 ppm max) and RC oscillator
32 kHz crystal (±50 ppm, ±500 ppm max) and
RCX oscillator
General purpose, Capture and Sleep timers
Digital interfaces
General purpose I/Os: 14 (WLCSP34 package),
24 (QFN40 package), 32 (QFN48 package)
2 UARTs with hardware flow control up to 1 MBd
SPI+™ interface
I2C bus at 100 kHz, 400 kHz
3-axes capable Quadrature Decoder
Analog interfaces
4-channel 10-bit ADC
Radio transceiver
Fully integrated 2.4 GHz CMOS transceiver
Single wire antenna: no RF matching or RX/TX
switching required
Supply current at VBAT3V:
TX: 3.4 mA, RX: 3.7 mA (with ideal DC-DC)
0 dBm transmit output power
-20 dBm output power in “Near Field Mode”
-93 dBm receiver sensitivity
Packages:
WLCSP 34 pins, 2.436 mm x 2.436 mm
QFN 40 pins, 5 mm x 5 mm
QFN 48 pins, 6 mm x 6 mm
KGD (wafer, dice)
System Diagram
Datasheet
CFR0011-120-01
Revision 3.4
1 of 155
09-Nov-2016
© 2014 Dialog Semiconductor
DA14580
Bluetooth Low Energy 4.2 SoC
Contents
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 8
4 System Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 ARM CORTEXM0 CPU . . . . . . . . . . . . . . . . . . 9
4.2 BLUETOOTH SMART . . . . . . . . . . . . . . . . . . . . 9
4.2.1 BLE Core . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2.2 Radio Transceiver . . . . . . . . . . . . . . . . . 10
4.2.3 SmartSnippets
4.3 MEMORIES . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.4 FUNCTIONAL MODES . . . . . . . . . . . . . . . . . . .11
4.5 POWER MODES. . . . . . . . . . . . . . . . . . . . . . . 12
4.6 INTERFACES . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.6.1 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.6.2 SPI+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.6.3 I2C Interface . . . . . . . . . . . . . . . . . . . . . 12
4.6.4 General Purpose ADC . . . . . . . . . . . . . . 13
4.6.5 Quadrature Decoder . . . . . . . . . . . . . . . 13
4.6.6 Keyboard Controller . . . . . . . . . . . . . . . . 13
4.6.7 Input/Output Ports . . . . . . . . . . . . . . . . . 13
4.7 TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.7.1 General Purpose Timers . . . . . . . . . . . . 13
4.7.2 Wake-Up timer . . . . . . . . . . . . . . . . . . . . 14
4.7.3 Watchdog Timer. . . . . . . . . . . . . . . . . . . 14
4.8 CLOCK/RESET . . . . . . . . . . . . . . . . . . . . . . . . 14
4.8.1 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.8.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.9 POWER MANAGEMENT . . . . . . . . . . . . . . . . 15
5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
7 Package Information . . . . . . . . . . . . . . . . . . . . . . . 151
7.1 MOISTURE SENSITIVITY LEVEL (MSL) . . . 151
7.2 WLCSP HANDLING . . . . . . . . . . . . . . . . . . . 151
7.3 SOLDERING INFORMATION . . . . . . . . . . . . 151
7.4 PACKAGE OUTLINES . . . . . . . . . . . . . . . . . 152
FINAL
Datasheet
CFR0011-120-00-FM
Revision 3.4
2 of 155
09-Nov-2016
© 2014 Dialog Semiconductor
DA14580
Bluetooth Low Energy 4.2 SoC
1
Block Diagram
FINAL
24 April 2012
ARM Cortex M0
XTAL
32.768 kHz
XTAL
16 MHz
DCDC
(BUCK/BOOST)
LDO
SYS
LDO
RET
LDO
LDO
LDO
SYS
SYS
RF
RC
16 MHz
RC
32 kHz
RCX
CORE
BLE Core
POReset
SWD (JTAG)
System/
Exchange
RAM
42 kB
AES-128
LINK LAYER
HARDWARE
Radio
Transceiver
Memory Controller
Ret. RAM2
3 kB
Ret. RAM3
2 kB
Ret. RAM4
1 kB
APB bridge
Ret. RAM
2 kB
POWER/CLOCK
Management (PMU)
KEYBOARD
CTRL
OTP
32 kB
ROM
84 kB
DMA
OTPC
FIFO
FIFO
Timer 2
3x PWM
GPIO MULTIPLEXING
Figure 1: DA14580 Block Diagram
Datasheet
CFR0011-120-01
Revision 3.4
3 of 155
FIFO
Timer 0
1x PWM
© 2014 Dialog Semiconductor
QUAD
DECODER
WAKE UP
TIMER
SW TIMER
GP ADC
UART2
UART
SPI
I2C
09-Nov-2016
DA14580
Bluetooth Low Energy 4.2 SoC
2
Pinout
The DA14580 comes in three packages:
• Wafer Level Chip Scale Package (WLCSP) with 34
balls
1
A
B
C
D
E
F
2
3
FI
O
m
R
FINAL
• Quad Flat Package No Leads (QFN) with 48 pins
• Quad Flat Package No Leads (QFN) with 40 pins
The actual pin/ball assignment is depicted in the follow-
ing figures:
4
FI
O
p
5
D
G
N
6
VP
P
38
37
VDCDC_RF
36
35
34
33
32
P2_5
XT
XT
AL
AL
16
16
M
M
m
p
VD
C
P1
D
C_
_3
R
F
R
LK
2
G
N
SW
_C
G
ND
2
P1
_
IO
P0
_
P1
_1
SW
D
VB
AT
1
_R
F
V
0
P0
_7
P0
_
G
N
VB
AT
Figure 2: WLCSP34 ball assignment
RFIOp
RFIOm
P2_8
P2_7
P3_7
P2_0
P2_9
47
48
46
45
44
43
42
41
40
P0_0
P0_1
P0_2
P0_3
P3_0
P0_4
P0_5
P2_1
P0_6
P3_1
P0_7
P3_2
1
2
3
4
5
6
7
8
9
10
11
12
39
P2_6
VPP
NC
XT
AL
32
Kp
XT
AL
32
Km
H
CD
C
C
G
N
D
VB
AT
3
SW
IT
VD
V
P0
_6
RS
T
P1
_
P0
_5
G
N
D
D
4
P0
_
3
P0
_0
P0
_1
D
P3_6
XTAL16Mm
XTAL16Mp
P1_3
P1_2
SW_CLK
SWDIO
P1_1
VBAT1V
P1_0
SWITCH
P3_5
DA14580
(Top View)
31
30
29
28
27
26
25
22
23
VDCDC
13
14
15
16
17
18
19
20
21
VBAT_RF
P3_3
P2_2
P3_4
XTAL32Km
XTAL32Kp
RST
P2_3
Figure 3: QFN48 Pin Assignment
Datasheet
CFR0011-120-01
Revision 3.4
4 of 155
VBAT3V
P2_4
GND
Pin 0: GND plane
24
09-Nov-2016
© 2014 Dialog Semiconductor
DA14580
Bluetooth Low Energy 4.2 SoC
VDCDC_RF
FINAL
RFIOm
RFIOp
P2_0
P2_9
P2_8
P2_7
P2_6
33
40
39
38
37
36
35
34
32
P2_5
VPP
P0_0
P0_1
P0_2
P0_3
NC
P0_4
P0_5
P2_1
P0_6
P0_7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
31
30
29
28
27
XTAL16Mm
XTAL16Mp
P1_3
P1_2
SW_CLK
SWDIO
P1_1
VBAT1V
P1_0
SWITCH
DA14580
(Top View)
26
25
24
23
22
21
VBAT_RF
VBAT3V
P2_2
XTAL32Km
XTAL32Kp
P2_3
VDCDC
Pin 0: GND
plane
Figure 4: QFN40 Pin Assignment
Table 1: Pin Description
Pin Name
Type
Drive
(mA)
4.8
Reset
State
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PU
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
Description
General Purpose I/Os
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
P1_0
P1_1
P1_2
P1_3
P1_4/SWCLK
P1_5/SW_DIO
P2_0
P2_1
P2_2
P2_3
P2_4
P2_5
P2_6
P2_7
P2_8
P2_9
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
INPUT/OUTPUT with selectable pull up/down resistor. Pull-down
enabled during and after reset. General purpose I/O port bit or
alternate function nodes. Contains state retention mechanism
during power down.
4.8
INPUT/OUTPUT with selectable pull up/down resistor. Pull-down
enabled during and after reset. General purpose I/O port bit or
alternate function nodes. Contains state retention mechanism
during power down.
This signal is the JTAG clock by default
This signal is the JTAG data I/O by default
INPUT/OUTPUT with selectable pull up/down resistor. Pull-down
enabled during and after reset. General purpose I/O port bit or
alternate function nodes. Contains state retention mechanism
during power down.
NOTE: This port is only available on the QFN40/QFN48 pack-
ages.
4.8
Datasheet
CFR0011-120-01
Revision 3.4
5 of 155
P2_4
GND
RST
09-Nov-2016
© 2014 Dialog Semiconductor
