DA14582
Bluetooth Low Energy 4.2 SoC with Audio CODEC
General Description
The DA14582 integrated circuit has a fully integrated
radio transceiver, baseband processor for
Bluetooth
®
low energy,
and includes an audio CODEC.
The DA14582 is optimized for remote control units
(RCU) requiring support for voice commands and
motion/gesture recognition. Its integrated analog wide
band audio CODEC provides native support for analog
microphones thereby reducing the total number of
components of the system while its optimized package
enables designs using single-layer FR1 PCBs further-
more contributing to the reduction of the cost of the
system.
The DA14582 supports a flexible memory architecture
for storing Bluetooth profiles and custom application
code, which can be updated over the air (OTA). The
qualified Bluetooth low energy protocol stack is stored
in a dedicated ROM. All software runs on the ARM
®
Cortex
®
-M0 processor via a simple scheduler.
The Bluetooth low energy firmware includes the
L2CAP service layer protocols, Security Manager
(SM), Attribute Protocol (ATT), the Generic Attribute
Profile (GATT) and the Generic Access Profile (GAP).
All profiles published by the Bluetooth SIG as well as
custom profiles are supported.
The transceiver interfaces directly to the antenna and
is fully compliant with the
Bluetooth 4.2
standard.
The DA14582 has dedicated hardware for the Link
Layer implementation of
Bluetooth
®
low energy
and
interface controllers for enhanced connectivity capabili-
ties.
FINAL
Features
Complies with
Bluetooth
V4.2, ETSI EN 300 328 and
EN 300 440 Class 2 (Europe), FCC CFR47 Part 15
(US) and ARIB STD-T66 (Japan)
Processing power
________________________________________________________________________________________________
16 MHz 32 bit ARM Cortex-M0 with SWD I/F
Dedicated Link Layer Processor
AES-128 bit encryption Processor
Memories
32 kB One-Time-Programmable (OTP) memory
42 kB System SRAM
84 kB ROM
8 kB Retention SRAM
Power management
Integrated Buck DC-DC converter
P0, P1, P2 and P3 ports with 3.3 V tolerance
Easy decoupling of only 4 supply pins
Supports coin (typ. 3.0 V) and alkaline (typ. 1.5 V)
battery cells
10-bit ADC for battery voltage measurement
Digital controlled oscillators
16 MHz crystal (±20 ppm max) and RC oscillator
32 kHz crystal (±50 ppm, ±500 ppm max) and
RCX oscillator
General purpose, Capture and Sleep timers
Digital interfaces
29 General purpose I/Os
2 UARTs with hardware flow control up to 1 MBd
SPI+™ interface
I2C bus at 100 kHz, 400 kHz
3-axis capable Quadrature Decoder
Analog interfaces
4-channel 10-bit ADC
14 bits wide band CODEC with microphone and
28
loudspeaker analog front-end
Radio transceiver
Fully integrated 2.4 GHz CMOS transceiver
Single wire antenna: no RF matching or RX/TX
switching required
Supply current at VBAT3V:
TX: 3.4 mA, RX: 3.7 mA (with ideal DC-DC)
0 dBm transmit output power
-20 dBm output power in “Near Field Mode”
-93 dBm receiver sensitivity
QFN 56 pins, 8 mm x 8 mm package
System Diagram
Datasheet
CFR0011-120-01
Revision 3.0
1 of 172
08-Nov-2016
© 2015 Dialog Semiconductor
DA14582
Bluetooth Low Energy 4.2 SoC with Audio CODEC
Contents
1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 8
4 System Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 ARM CORTEXM0 CPU . . . . . . . . . . . . . . . . . . 9
4.2 BLUETOOTH SMART . . . . . . . . . . . . . . . . . . . . 9
4.2.1 BLE Core . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2.2 Radio Transceiver . . . . . . . . . . . . . . . . . 10
4.2.3 SmartSnippets
4.3 MEMORIES . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.4 FUNCTIONAL MODES . . . . . . . . . . . . . . . . . . .11
4.5 POWER MODES. . . . . . . . . . . . . . . . . . . . . . . 12
4.6 INTERFACES . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.6.1 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.6.2 SPI+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.6.3 I2C Interface . . . . . . . . . . . . . . . . . . . . . 12
4.6.4 General Purpose ADC . . . . . . . . . . . . . . 13
4.6.5 Quadrature Decoder . . . . . . . . . . . . . . . 13
4.6.6 Keyboard Controller . . . . . . . . . . . . . . . . 13
4.6.7 Input/Output Ports . . . . . . . . . . . . . . . . . 13
4.7 TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.7.1 General Purpose Timers . . . . . . . . . . . . 13
4.7.2 Wake-Up Timer . . . . . . . . . . . . . . . . . . . 14
4.7.3 Watchdog Timer. . . . . . . . . . . . . . . . . . . 14
4.8 CLOCK/RESET . . . . . . . . . . . . . . . . . . . . . . . . 14
4.8.1 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.8.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.9 POWER MANAGEMENT . . . . . . . . . . . . . . . . 15
4.10 AUDIO CODEC WITH ANALOG FRONTEND17
5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6 CODEC Registers . . . . . . . . . . . . . . . . . . . . . . . . . 138
7 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
8 CODEC Specifications . . . . . . . . . . . . . . . . . . . . . 159
8.1 CODEC DC CHARACTERISTICS . . . . . . . . 159
8.2 ANALOG FRONTEND SPECIFICATIONS . . 161
8.3 CODEC AC CHARACTERISTICS . . . . . . . . 165
8.4 CODEC TIMING CHARACTERISTICS . . . . . 169
9 Package Information . . . . . . . . . . . . . . . . . . . . . . . 170
9.1 MOISTURE SENSITIVITY LEVEL (MSL) . . . 170
9.2 SOLDERING INFORMATION . . . . . . . . . . . . 170
9.3 PACKAGE OUTLINES . . . . . . . . . . . . . . . . . 171
FINAL
Datasheet
CFR0011-120-01
Revision 3.0
2 of 172
08-Nov-2016
© 2015 Dialog Semiconductor
DA14582
Bluetooth Low Energy 4.2 SoC with Audio CODEC
1
Block Diagram
FINAL
24 April 2012
ARM Cortex M0
XTAL
32.768 kHz
XTAL
16 MHz
LDO
SYS
DC-DC
(BUCK)
LDO
RET
LDO
LDO
LDO
SYS
SYS
RF
RC
16 MHz
RC
32 kHz
RCX
CORE
BLE Core
POReset
SWD (JTAG)
System/
Exchange
RAM
42 kB
AES-128
LINK LAYER
HARDWARE
Radio
Transceiver
Memory Controller
Ret. RAM2
3 kB
Ret. RAM3
2 kB
Ret. RAM4
1 kB
APB bridge
Ret. RAM
2 kB
POWER/CLOCK
Management (PMU)
KEYBOARD
CTRL
QUAD
DECODER
WAKE UP
TIMER
SW TIMER
GP ADC
OTP
32 kB
ROM
84 kB
DMA
OTPC
FIFO
FIFO
Timer 2
3x PWM
GPIO MULTIPLEXING
Figure 1: DA14582 Block Diagram
Datasheet
CFR0011-120-01
Revision 3.0
3 of 172
FIFO
Timer 0
1x PWM
08-Nov-2016
© 2015 Dialog Semiconductor
CODEC
UART2
UART
SPI
I2C
DA14582
Bluetooth Low Energy 4.2 SoC with Audio CODEC
2
Pinout
FINAL
VDCDC_RF
RFIOm
RFIOp
P0_1
P0_0
P2_0
P2_9
P2_8
P2_7
P3_7
P2_6
P2_5
P3_6
VPP
Pin 58: GND plane
56
55
53
51
50
49
48
47
46
45
44
54
52
43
P0_2
P0_3
P3_0
P0_4/SPI_DI
P0_5/16MCLK
P0_6
P2_1/SPI_EN
P0_7
VDDIO
GPIO2
GPIO3
RSTn
VDD
LSRn
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
25
24
26
27
42
41
40
39
38
37
XTAL16Mm
XTAL16Mp
P1_3
P1_2
SW_CLK
SWDIO
P1_1
VBAT1V
P1_0
SWITCH
P3_5
P2_4
VDCDC
P2_3
DA14582
(top view)
36
35
34
33
32
31
30
29
28
RST
Pin 57: GND plane
XTAL32Km
XTAL32Kp
VBAT_RF
VBAT3V
VREFm
MICp
MICp
VREFp
P3_3
LSRp
VBUF
P2_2
GND
Figure 2: QFN56 Pin Assignment
Datasheet
CFR0011-120-01
Revision 3.0
4 of 172
08-Nov-2016
© 2015 Dialog Semiconductor
DA14582
Bluetooth Low Energy 4.2 SoC with Audio CODEC
FINAL
Table 1: Pin Description
Pin Name
Type
Drive
(mA)
4.8
Reset
State
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PU
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PU
I-PD
Description
General Purpose I/Os
P0_0
P0_1
P0_2
P0_3/
P0_4/SPI_DI
P0_5/16MCLK
P0_6
P0_7
P1_0
P1_1
P1_2
P1_3
P1_4/SWCLK
P1_5/SW_DIO
P2_0
P2_1/SPI_EN
P2_2
P2_3
P2_4
P2_5
P2_6
P2_7
P2_8
P2_9
P3_0
P3_1 (Table
2)
P3_2 (Table
2)
P3_3
P3_5
P3_6
P3_7
Debug Interface
SW_DIO/P1_5
SW_CLK/P1_4
Clocks
XTAL16Mp
XTAL16Mm
XTAL32kp
XTAL32km
AI
AO
AI
AO
INPUT. Crystal input for the 16 MHz XTAL
OUTPUT. Crystal output for the 16 MHz XTAL
INPUT. Crystal input for the 32.768 kHz XTAL
OUTPUT. Crystal output for the 32.768 kHz XTAL
DIO
DIO
4.8
4.8
INPUT/OUTPUT. JTAG Data input/output. Bidirectional data and
control communication. Can also be used as a GPIO
INPUT JTAG clock signal. Can also be used as a GPIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
INPUT/OUTPUT with selectable pull up/down resistor. Pull-
down enabled during and after reset. General purpose I/O port
bit or alternate function nodes. Contains state retention mecha-
nism during power down.
4.8
INPUT/OUTPUT with selectable pull up/down resistor. Pull-
down enabled during and after reset. General purpose I/O port
bit or alternate function nodes. Contains state retention mecha-
nism during power down.
This signal is the JTAG clock by default
This signal is the JTAG data I/O by default
INPUT/OUTPUT with selectable pull up/down resistor. Pull-
down enabled during and after reset. General purpose I/O port
bit or alternate function nodes. Contains state retention mecha-
nism during power down.
4.8
4.8
INPUT/OUTPUT with selectable pull up/down resistor. Pull-
down enabled during and after reset. General purpose I/O port
bit or alternate function nodes. Contains state retention mecha-
nism during power down.
Datasheet
CFR0011-120-01
Revision 3.0
5 of 172
08-Nov-2016
© 2015 Dialog Semiconductor
RF/无线
