DAC1405D650
Dual 14-bit DAC, up to 650 Msps; 2, 4 and 8 interpolating
Rev. 05 — 2 July 2012
Product data sheet
1. General description
The DAC1405D650 is a high-speed 14-bit dual channel Digital-to-Analog Converter
(DAC) with selectable 2, 4 or 8 interpolating filters optimized for multi-carrier wireless
transmitters.
Thanks to its digital on-chip modulation, the DAC1405D650 allows the complex I and Q
inputs to be converted up from baseband to IF. The mixing frequency is adjusted via a
Serial Peripheral Interface (SPI) with a 32-bit Numerically Controlled Oscillator (NCO) and
the phase is controlled by a 16-bit register.
Two modes of operation are available: separate data ports or a single interleaved
high-speed data port. In the Interleaved mode, the input data stream is demultiplexed into
its original I and Q data and then latched.
The DAC1405D650 also includes a 2, 4 and 8 clock multiplier which provides the
appropriate internal clocks and an internal regulator to adjust the output full-scale current.
2. Features and benefits
Dual 14-bit resolution
650 Msps maximum update rate
IMD3: 80 dBc; f
s
= 640 Msps; f
o
= 96 MHz
ACPR: 71 dBc; 2 carriers WCDMA;
f
s
= 614.4 Msps; f
o
= 96 MHz; PLL on
Selectable 2, 4 or 8 interpolation
Typical 0.95 W power dissipation at 4
filters
interpolation
Input data rate up to 160 Msps
Power-down and Sleep modes
Very low noise cap-free integrated PLL
Differential scalable output current from
1.6 mA to 22 mA
32-bit programmable NCO frequency
On-chip 1.29 V reference
Dual port or Interleaved data modes
External analog offset control
(10-bit auxiliary DACs)
1.8 V and 3.3 V power supplies
Internal digital offset control
LVDS compatible clock
Inverse (sin x) / x function
Two’s complement or binary offset
Fully compatible SPI port
data format
3.3 V CMOS input buffers
Industrial temperature range from
40 C
to +85
C
®
Integrated Device Technology
DAC1405D650
Dual 14-bit DAC, up to 650 Msps; 2, 4 and 8 interpolating
3. Applications
Wireless infrastructure: LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA
Communication: LMDS/MMDS, point-to-point
Direct Digital Synthesis (DDS)
Broadband wireless systems
Digital radio links
Instrumentation
Automated Test Equipment (ATE)
4. Ordering information
Table 1.
Ordering information
Package
Name
DAC1405D650HW
HTQFP100
Description
plastic thermal enhanced thin quad flat package; 100 leads;
body 14
14
1 mm; exposed die pad
Version
SOT638-1
Type number
DAC1405D650 5
© IDT 2012. All rights reserved.
Product data sheet
Rev. 05 — 2 July 2012
2 of 41
5. Block diagram
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Product data sheet
Rev. 05 — 2 July 2012
3 of 41
DAC1405D650 5
© IDT 2012. All rights reserved.
Integrated Device Technology
SDO
SDIO
SCS_N
SCLK
SPI
Cos
NCO
Sin
mixer
10-BIT
OFFSET
CONTROL
10-BIT
GAIN
CONTROL
+
AUX.
DAC
AUXAP
AUXAN
DAC1405D650
FIR1
I0 to I13
14
FIR2
2
×
FIR3
2
×
mixer
−
A
LATCH
I
x
sin x
+
DAC
IOUTAP
IOUTAN
2
×
Dual 14-bit DAC, up to 650 Msps; 2, 4 and 8 interpolating
dual port/
interleaved
data modes
FIR1
LATCH
Q
Q0 to Q13
14
+
OFFSET
CONTROL
FIR2
2
×
FIR3
2
×
mixer
REFERENCE
BANDGAP
VIRES
GAPOUT
2
×
+
B
x
sin x
+
DAC
IOUTBP
IOUTBN
CLKP
CLKN
CLOCK GENERATOR/
PLL
mixer
10-BIT
GAIN
CONTROL
COMPLEX MODULATOR
10-BIT
OFFSET
CONTROL
AUX.
DAC
AUXBP
AUXBN
001aah069
DAC1405D650
RESET_N
Fig 1.
Block diagram
Integrated Device Technology
DAC1405D650
Dual 14-bit DAC, up to 650 Msps; 2, 4 and 8 interpolating
6. Pinning information
6.1 Pinning
99 V
DDA(1V8)
97 V
DDA(1V8)
95 V
DDA(1V8)
93 V
DDA(1V8)
83 V
DDA(1V8)
81 V
DDA(1V8)
79 V
DDA(1V8)
77 V
DDA(1V8)
91 IOUTAN
85 IOUTBN
90 IOUTAP
86 IOUTBP
80 AGND
98 AGND
96 AGND
92 AGND
100 AGND
78 AGND
94 AGND
89 AGND
87 AGND
84 AGND
82 AGND
V
DDA(3V3)
AUXAP
AUXAN
AGND
V
DDA(1V8)
V
DDA(1V8)
AGND
CLKP
CLKN
1
2
3
4
5
6
7
8
9
76 AGND
88 n.c.
75 V
DDA(3V3)
74 AUXBP
73 AUXBN
72 AGND
71 V
DDA(1V8)
70 V
DDA(1V8)
69 GAPOUT
68 VIRES
67 d.n.c.
66 RESET_N
65 SCS_N
64 SCLK
AGND 10
V
DDA(1V8)
11
d.n.c. 12
d.n.c. 13
TM1 14
TM0 15
V
DD(IO)(3V3)
16
GNDIO 17
I13 18
I12 19
I11 20
I10 21
I9 22
I8 23
I7 24
I6 25
AGND
DAC1405D650HW
63 SDIO
62 SDO
61 TM3
60 V
DD(IO)(3V3)
59 GNDIO
58 Q0
57 Q1
56 Q2
55 Q3
54 Q4
53 Q5
52 Q6
51 Q7
V
DDD(1V8)
26
DGND 27
I5 28
I4 29
I3 30
I2 31
V
DDD(1V8)
32
DGND 33
I1 34
I0 35
V
DDD(1V8)
36
DGND 37
TM2 38
DGND 39
V
DDD(1V8)
40
Q13/SELIQ 41
Q12 42
DGND 43
V
DDD(1V8)
44
Q11 45
Q10 46
Q9 47
Q8 48
DGND 49
V
DDD(1V8)
50
001aah075
Fig 2.
Pin configuration
DAC1405D650 5
© IDT 2012. All rights reserved.
Product data sheet
Rev. 05 — 2 July 2012
4 of 41
Integrated Device Technology
DAC1405D650
Dual 14-bit DAC, up to 650 Msps; 2, 4 and 8 interpolating
6.2 Pin description
Table 2.
Symbol
V
DDA(3V3)
AUXAP
AUXAN
AGND
V
DDA(1V8)
V
DDA(1V8)
AGND
CLKP
CLKN
AGND
V
DDA(1V8)
d.n.c.
d.n.c.
TM1
TM0
V
DD(IO)(3V3)
GNDIO
I13
I12
I11
I10
I9
I8
I7
I6
V
DDD(1V8)
DGND
I5
I4
I3
I2
V
DDD(1V8)
DGND
I1
I0
V
DDD(1V8)
DGND
TM2
DGND
DAC1405D650 5
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
Type
[1]
P
O
O
G
P
P
G
I
I
G
P
-
-
I/O
I/O
P
G
I
I
I
I
I
I
I
I
P
G
I
I
I
I
P
G
I
I
P
G
-
G
Description
analog supply voltage 3.3 V
auxiliary DAC B output current
complementary auxiliary DAC B output current
analog ground
analog supply voltage 1.8 V
analog supply voltage 1.8 V
analog ground
clock input
complementary clock input
analog ground
analog supply voltage 1.8 V
do not connect
do not connect
test mode 1 (to connect to DGND)
test mode 0 (to connect to DGND)
input/output buffers supply voltage 3.3 V
input/output buffers ground
I data input bit 13 (MSB)
I data input bit 12
I data input bit 11
I data input bit 10
I data input bit 9
I data input bit 8
I data input bit 7
I data input bit 6
digital supply voltage 1.8 V
digital ground
I data input bit 5
I data input bit 4
I data input bit 3
I data input bit 2
digital supply voltage 1.8 V
digital ground
I data input bit 1
I data input bit 0 (LSB)
digital supply voltage 1.8 V
digital ground
test mode 2 (to connect to DGND)
digital ground
© IDT 2012. All rights reserved.
Product data sheet
Rev. 05 — 2 July 2012
5 of 41
电源技术
