a
FEATURES
Compact SOIC, and TSSOP Packages
True 12-Bit Accuracy
5 V Operation @ <10 A
Fast 3-Wire Serial Input
Fast 1 s Settling Time
2.4 MHz 4-Quadrant Multiply BW
Pin-for-Pin Upgrade for DAC8043
Standard and Rotated Pinout
APPLICATIONS
Ideal for PLC Applications in Industrial Control
Programmable Amplifiers and Attenuators
Digitally Controlled Calibration and Filters
Motion Control Systems
12-Bit Serial Input
Multiplying D/A Converter
DAC8043A
FUNCTIONAL BLOCK DIAGRAM
DAC8043A
V
DD
V
REF
DAC
12
LD
DAC REG
12
CLK
SRI
GND
12-BIT SHIFT
REGISTER
R
FB
I
OUT
GENERAL DESCRIPTION
0.5
0.4
0.3
0.2
T
A
= +25 C, +85 C, –40 C
V
DD
= +5V
V
REF
= –10V
The DAC8043A is an improved high accuracy 12-bit multiply-
ing digital-to-analog converter in space-saving 8-lead packages.
Featuring serial input, double buffering and excellent analog
performance, the DAC8043A is ideal for applications where PC
board space is at a premium. Improved linearity and gain error
performance permit reduced parts count through the elimina-
tion of trimming components. Separate input clock and load
DAC control lines allow full user control of data loading and
analog output.
The circuit consists of a 12-bit serial-in/parallel-out shift regis-
ter, a 12-bit DAC register, a 12-bit CMOS DAC and control
logic. Serial data is clocked into the input register on the rising
edge of the CLOCK pulse. When the new data word has been
clocked in, it is loaded into the DAC register with the
LD
input
pin. Data in the DAC register is converted to an output current
by the D/A converter.
Consuming only 10
µA
from a single 5 V power supply, the
DAC8043A is the ideal low power, small size, high performance
solution to many application problems.
The DAC8043A is specified over the extended industrial
(–40°C to +85°C) temperature range. DAC8043A is available
in a PDIP package, and the low profile 1.75 mm height SOIC-8
surface mount packages. The DAC8043AFRU is available for
ultra-compact applications in a thin 1.1 mm TSSOP-8 package.
INL – LSB
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
512
1024
1536
2048
CODE
2560
3072
3584
4096
Figure 1. Integral Nonlinearity Error vs. Code
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/461-3113
© Analog Devices, Inc., 2006
DAC8043A–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter
STATIC PERFORMANCE
Resolution
Relative Accuracy
Differential Nonlinearity
Gain Error
1
Gain Tempco
2
Output Leakage Current
Zero-Scale Error
3
REFERENCE INPUT
Input Resistance
Input Capacitance
2
ANALOG OUTPUT
Output Capacitance
2
DIGITAL INPUTS
Digital Input Low
Digital Input High
Input Leakage Current
Input Capacitance
2
INTERFACE TIMING
2, 4
Data Setup
Data Hold
Clock Width High
Clock Width Low
Load Pulsewidth
LSB CLK to
LD
DAC
AC CHARACTERISTICS
1, 2
Output Current Settling Time
DAC Glitch
Feedthrough (V
OUT
/V
REF
)
Total Harmonic Distortion
Output Noise Density
5
Multiplying Bandwidth
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
Power Dissipation
Power Supply Sensitivity
Symbol
N
INL
DNL
G
FSE
TCG
FS
I
LKG
I
ZSE
(@ V
DD
= 5 V, V
REF
= 10 V, –40 C < T
A
< +85 C, unless otherwise noted.)
E Grade F Grade Unit
12
±
1.0
±
1.0
±
2.0
±
2.0
±
5
±
5
±
25
0.03
0.15
7/15
5
25
30
0.8
2.4
0.001/± 1
10
10
5
25
25
25
0
1
20
1
–85
17
2.4
4.5/5.5
10
50
0.002
Bits
LSB max
LSB max
LSB max
LSB max
ppm/°C max
nA max
nA max
LSB max
LSB max
kΩ min/max
pF typ
pF typ
pF typ
V max
V min
µA
typ/max
pF max
ns min
ns min
ns min
ns min
ns min
ns min
µs
max
nVs max
mV p-p
dB typ
nV/√Hz max
MHz typ
V min/max
µA
max
µW
max
%/% max
Condition
12
±
0.5
All Grades Monotonic to 12 Bits
±
0.5
T
A
= 25°C, Data = FFF
H
±
1.0
T
A
= –40°C, +85°C, Data = FFF
H
±
2.0
I
OUT
Pin Measured
±
5
Data = 000
H
, I
OUT
Pin Measured
±
5
T
A
= –40°C, +85°C, Data = 000
H
, I
OUT
Pin Measured
±
25
Data = 000
H
0.03
T
A
= –40°C, +85°C, Data = 000
H
0.15
Absolute Tempco < 50 ppm/°C
7/15
5
25
30
0.8
2.4
0.001/± 1
10
10
5
25
25
25
0
To
±
0.01% of Full Scale, Ext Op Amp OP42
Data = 000
H
to FFF
H
to 000
H
, V
REF
= 0 V
V
REF
= 20 V p-p, Data = 000
H
, f = 10 kHz
V
REF
= 6 V rms, Data = FFF
H
, f = 1 kHz
10 Hz to 100 kHz Between R
FB
and I
OUT
–3 dB, V
OUT
/V
REF
, V
REF
= 100 mV rms, Data = FFF
H
1
20
1
–85
17
2.4
4.5/5.5
10
50
0.002
R
REF
C
REF
C
OUT
Data = 000
H
Data = FFF
H
V
IL
V
IH
I
IL
C
IL
t
DS
t
DH
t
CH
t
CL
t
LD
t
ASB
t
S
Q
FT
THD
e
n
BW
V
DD RANGE
I
DD
P
DISS
PSS
V
LOGIC
= 0 V to 5 V
V
LOGIC
= 0 V
V
LOGIC
= 0 V or V
DD
V
LOGIC
= 0 V or V
DD
∆V
DD
=
±
5%
NOTES
1
Using internal feedback resistor R
FB
, see Figure 19 test circuit with V
REF
= 10 V.
2
These parameters are guaranteed by design and not subject to production testing.
3
Calculated from worst case R
REF
: I
ZSE
(LSB) = (R
REF
×
I
LKG
×
4096)/V
REF
.
4
All input control signals are specified with t
R
= t
F
= 2 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
5
Calculation from e
n
=
√4KTRB
where: K = Boltzmann Constant (J/°K), R = Resistance (Ω), T = Resistor Temperature (°K), B = 1 Hz Bandwidth.
Specifications subject to change without notice.
–2–
REV. B
DAC8043A
ABSOLUTE MAXIMUM RATINGS*
PIN FUNCTION DESCRIPTIONS
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V
V
REF
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
18 V
R
FB
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
18 V
Logic Inputs to GND . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
VI
OUT
to GND . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
I
OUT
Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . 50 mA
Package Power Dissipation . . . . . . . . . . . . . (T
J
max – T
A
)/θ
JA
Thermal Resistance
θ
JA
8-Lead PDIP Package (N-8) . . . . . . . . . . . . . . . . . 103°C/W
8-Lead SOIC Package (R-8) . . . . . . . . . . . . . . . . . 158°C/W
8-Lead TSSOP Package (RU-8) . . . . . . . . . . . . . . 240°C/W
Maximum Junction Temperature (T
J
max) . . . . . . . . . 150°C
Operating Temperature Range . . . . . . . . . . – 40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C
*Stresses
above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
#(*) Name Function
1(7)
V
REF
DAC Reference Input Pin. Establishes DAC full-
scale voltage. Constant input resistance versus
code.
Internal Matching Feedback Resistor. Connect
to external op amp output.
DAC Current Output, full-scale output 1 LSB
less than reference input voltage –V
REF
.
Analog and Digital Ground.
Load Strobe, Level-Sensitive Digital Input.
Transfers shift-register data to DAC register
while active low. See truth table for operation.
12-Bit Serial Register Input, data loads directly
into the shift register MSB first. Extra leading
bits are ignored.
Clock Input, positive-edge clocks data into shift
register.
Positive Power Supply Input. Specified range of
operation 5 V
±
10%.
2 (8) R
FB
3 (1) I
OUT
4 (2) GND
5 (3)
LD
6 (4) SRI
7 (5) CLK
8 (6) V
DD
ORDERING GUIDE
*Note
Pin numbers in parenthesis represent the rotated pinout of the
DAC8043A1ES and DAC8043A1FS models.
DAC8043AE/F PIN CONFIGURATIONS
V
REF
1
R
FB
2
1
4
8
5
8
V
DD
1
4
8
5
7
CLK
TOP VIEW
I
OUT
3
(Not to Scale)
6
SRI
GND
4
5
LD
TSSOP-8
DAC8043A
FRU
SOIC-8
DAC8043A
ES/FS
PDIP-8
DAC8043A
EP/FP
DAC8043A1E AND DAC8043A1F PIN CONFIGURATION
(Rotated Pinout)
I
OUT
1
GND
2
8
R
FB
7
V
REF
TOP VIEW
LD
3
(Not to Scale)
6
V
DD
5
SRI
4
SOIC-8
CLK
DAC8043A1ES
DAC8043A1FS
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the DAC8043A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–3–
DAC8043A
SRI
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CLK
t
LD1
LD
DATA LOADED MSB(D11) FIRST
DAC REGISTER LOAD
t
ASB
SRI
Dxx
t
DS
CLK
t
DH
t
CH
t
LD
t
S
t
CL
LD
FS
V
OUT
ZS
1 LSB
ERROR BAND
Figure 2. Timing Diagram
Table I. Control-Logic Truth Table
CLK
u
H or L
L
LD
H
L
u
Serial Shift Register Function
DAC Register Function
Shift-Register-Data Advanced One Bit Latched
No Effect
Updated with Current Shift Register Contents
No Effect
Latched All 12 Bits
NOTES
u
positive logic transition.
The DAC Register
LD
input is level-sensitive. Any time
LD
is logic-low data in the serial register will directly control the
switches in the R-2R DAC ladder.
Typical Performance Characteristics
35
30
25
SS = 200 UNITS
T
A
= 25 C
V
DD
= 5V
V
REF
= 10V
50
SS = 200 UNITS
T
A
= –40 C TO +85 C
V
DD
= 5V
V
REF
= 10V
40
FREQUENCY
FREQUENCY
20
30
15
10
20
10
5
0
–1.0
–0.5
0.0
0.5
TOTAL UNADJUSTED ERROR – LSB
1.0
0
0
1
FULL SCALE TEMPCO – ppm/ C
2
Figure 3. Total Unadjusted Error Histogram
Figure 4. Full-Scale Output Tempco Histogram
–4–
REV. B
DAC8043A
0.5
100
V
DD
= 5V
10%
SUPPLY CURRENT I
DD
– mA
0.4
T
A
= 25 C
V
DD
= 5V
80
0.3
PSRR – dB
60
0.2
40
0.1
0
0
0.5
1
1.5
2.5
3.5
2
3
LOGIC INPUT VOLTAGE – Volts
4
4.5
5
20
1k
10k
100k
FREQUENCY – Hz
1M
10M
Figure 5. Supply Current vs. Logic Input Voltage
Figure 8. Power Supply Rejection vs. Frequency
10
V
DD
= 5V
V
LOGIC
= 0V OR V
DD
1
0.5
0.4
0.3
0.2
DNL – LSB
V
DD
= 5V
V
REF
= 10V
SUPERIMPOSED: T
A
= –40 C, +25 C, +85 C
I
DD
– A
0.1
0
–0.1
–0.2
0.1
0.01
–0.3
–0.4
0.001
–55
–35
–15
5
25
45
65
TEMPERATURE – C
85
105
125
–0.5
0
512
1024
2048 2560
1536
CODE – Decimal
3072
3584
4096
Figure 6. Supply Current vs. Temperature
Figure 9. Linearity Error vs. Digital Code
3500
3000
2500
CODE = F55H
2000
1500
CODE = 800H
1000
CODE = FFFH
500
0
1k
V
DD
= 5V
V
REF
= 10V
T
A
= 25 C
4
V
DD
= 5V
V
REF
= 10V
T
A
= 25 C
2
INL – LSB
I
DD
– A
0
–2
10k
100k
1M
FREQUENCY – Hz
10M
100M
–4
–2000
–1000
0
1000
OPAMP OFFSET V
OS
– V
2000
Figure 7. Supply Current vs. Clock Frequency
Figure 10. Linearity Error vs. External Op Amp V
OS
REV. B
–5–
ARM技术
