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FEATURES

Two Matched 12-Bit DACs on One Chip

Direct Parallel Load of All 12 Bits for High Data

Throughput

Double-Buffered Digital Inputs

12-Bit Endpoint Linearity ( 1/2 LSB) Over Temperature

+5 V to +15 V Single Supply Operation

DACs Matched to 1% Max

Four-Quadrant Multiplication

Improved ESD Resistance

Packaged in a Narrow 0.3" 24-Lead DIP and 0.3"

24- Lead SOL Package

Available in Die Form

APPLICATIONS

Automatic Test Equipment

Robotics/Process Control/Automation

Digital Gain/Attenuation Control

Ideal for Battery-Operated Equipment

Dual 12-Bit Double-Buffered

Multiplying CMOS D/A Converter

DAC8222

FUNCTIONAL DIAGRAM

GENERAL DESCRIPTION

The DAC8222 is a dual 12-bit, double-buffered, CMOS digital-

to-analog converter. It has a 12-bit wide data port that allows a

12-bit word to be loaded directly. This achieves faster through-

put time in stand-alone systems or when interfacing to a 16-bit

processor. A common 12-bit input TTL/CMOS compatible

data port is used to load the 12-bit word into either of the two

DACs. This port, whose data loading is similar to that of a RAM’s

write cycle, interfaces directly with most 12-bit and 16-bit bus

systems. (See DAC8248 for a complete 8-bit data bus interface

product.) A common bus allows the DAC8222 to be packaged

in a narrow 24-lead 0.3" DIP and save PCB space.

The DAC is controlled with two signals,

and

LDAC.

With

logic low at these inputs, the DAC registers become transparent.

This allows direct unbuffered data to flow directly to either

DAC output selected by

DAC A/DAC

B. Also, the DAC’s

double-buffered digital inputs will allow both DACs to be

simultaneously updated.

DAC8222’s monolithic construction offers excellent DAC-to-

DAC matching and tracking over the full operating tempera-

ture range. The chip consists of two thin-film R-2R resistor

ladder networks, four 12-bit registers, and DAC control logic

circuitry. The device has separate reference-input and feedback

resistors for each DAC and operates on a single supply from

+5 V to +15 V. Maximum power dissipation at +5 V using

zero or V

logic levels is less than 0.5 mW.

The DAC8222 is manufactured with highly stable thin-film re-

sistors on an advanced oxide-isolated, silicon-gate, CMOS

technology. Improved latch-up resistant design eliminates the

need for external protective Schottky diodes.

REV. C

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

DAC8222–SPECIFICATIONS

(@ V

= +5 V or +15 V, V

REF A

= V

REF B

= +10 V, V

OUT A

= V

OUT B

= 0 V; AGND = DGND = 0 V;

= Full Temperature Range Specified in Absolute Maximum Ratings; unless otherwise noted. Specifications apply for DAC A and DAC B.)

Parameter

STATIC ACCURACY

Resolution

Relative Accuracy

Differential Nonlinearity

Full-Scale Gain Error

Gain Temperature Coefficient

∆Gain/∆Temperature

Output Leakage Current

OUT A

(Pin 2),

OUT B

(Pin 24)

Input Resistance

REF A

, V

REF B

)

Input Resistance Match

DIGITAL INPUTS

Digital Input High

Digital Input Low

Input Current

Input Capacitance

POWER SUPPLY

Supply Current

DC Power Supply

Rejection Ratio

(∆Gain/∆V

)

Symbol Conditions

INL

DNL

FSE

Min

DAC8222A/E/G

DAC8222F/H

All Grades are Guaranteed Monotonic

DAC8222A/E

DAC8222G

DAC8222F/H

(Notes 2, 7)

All Digital Inputs =

0000 0000 0000

(Note 9)

= +25°C

= Full Temp. Range

0.2

Endpoint Linearity Error

Typ

Max

Units

Bits

LSB

ppm/°C

kΩ

ELECTRICAL CHARACTERISTICS

1/2

TCG

LKG

REF

∆R

REF

INH

INL

= +5 V

= +15 V

= +5 V

= +15 V

= 0 V or V

= +25°C

= Full Temp. Range

and V

INL

or V

INH

DB0–DB11

WR, LDAC, DAC A/DAC

All Digital Inputs V

INL

or V

INH

All Digital Inputs 0 V or V

∆V

2.4

13.5

0.001

0.8

1.5

100

0.002

µA

%/%

PSRR

AC PERFORMANCE CHARACTERISTICS

Propagation Delay

4, 5

= +25°C

5, 6

= +25°C

Current Settling Time

Digital Inputs = All 0s

Output Capacitance

OUT A

, C

OUT B

Digital Inputs = All 1s

OUT A

, C

OUT B

REF A

to I

OUT A

; V

REF A

= 20 V p-p;

AC Feedthrough at

f = 100 kHz; T

= +25°C

OUT A

or I

OUT B

REF B

to I

OUT B

; V

REF B

= 20 V p-p;

f = 100 kHz; T

= +25°C

SWITCHING CHARACTERISTICS

2, 3

DAC Select to

Write Set-Up Time

DAC Select to

Write Hold Time

LDAC

Write Set-Up Time

LDAC

Write Hold Time

Data Valid to

Write Set-Up Time

Data Valid to

Write Hold Time

Write Pulse Width

LDAC

Pulse Width

LWD

+25°C

150

220

130

100

350

120

–70

µs

= +5 V

= +15 V

–40°C to +85°C –55°C to +125°C All Temps

180

210

100

240

160

120

260

170

130

100

ns min

NOTES

Measured using internal R

FB A

and R

FB B

. Both DAC digital inputs = 1111 1111 1111.

Guaranteed and not tested.

See timing diagram.

From 50% of digital input to 90% of final analog output current.

REF A

= V

REF B

= +10 V; OUT A, OUT B load = 100

Ω,

EXT

= 13 pF.

WR, LDAC

= 0 V; DB0–DB11 = 0 V to V

or V

to 0 V.

Settling time is measured from 50% of the digital input change to where the

output voltage settles within 1/2 LSB of full scale.

Gain TC is measured from +25°C to T

MIN

or from +25°C to T

MAX

These limits apply for the commercial and industrial grade products.

Absolute temperature coefficient is approximately +50 ppm/°C.

These limits also apply as typical values for V

= +12 V with +5 V CMOS

logic levels and T

= +25°C.

Specifications subject to change without notice.

–2–

REV. C

DAC8222

ABSOLUTE MAXIMUM RATINGS

= +25°C, unless otherwise noted.)

PIN CONNECTIONS

24-Lead 0.3" Cerdip

24-Lead Plastic DIP

24-Lead SOL

28-Terminal LCC

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V

AGND to DGND . . . . . . . . . . . . . . . . . . –0.3 V, V

+0.3 V

Digital Input Voltage to DGND . . . . . . . –0.3 V, V

+0.3 V

OUTA

, I

OUTB

to AGND . . . . . . . . . . . . . . –0.3 V, V

+0.3 V

REFA

, V

REFB

to AGND . . . . . . . . . . . . . . . . . . . . . . . . .

25 V

RFBA

, V

RFBB

to AGND . . . . . . . . . . . . . . . . . . . . . . . . .

25 V

Operating Temperature Range

AW Version . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C

EW, FW, FP Versions . . . . . . . . . . . . . . . . –40°C to +85°C

GP, HP, HS Versions . . . . . . . . . . . . . . . . . . . 0°C to +70°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300°C

Package Type

24-Lead Hermetic DIP (W)

24-Lead Plastic DIP (P)

24-Lead SOL (S)

NC = NO CONNECT

Units

°C/W

NOTE

is specified for worst-case mounting conditions, i.e., q

is specified for

device in socket for Cerdip, and P-DIP packages;

is specified for device

soldered to printed circuit board for SO package.

CAUTION

1. Do not apply voltages higher than V

or less than GND

potential on any terminal except V

REF

and R

2. The digital control inputs are Zener-protected; however,

permanent damage may occur on unprotected units from

high-energy electrostatic fields. Keep units in conductive

foam at all times until ready to use.

3. Do not insert this device into powered sockets; remove

power before insertion or removal.

4. Use proper antistatic handling procedures.

5. Devices can suffer permanent damage and/or reliability deg-

radation if stressed above the limits listed under Absolute

Maximum Ratings for extended periods.

ORDERING GUIDE

Model

DAC8222EW

DAC8222GP

DAC8222BTC/883*

DAC8222FW

DAC8222FP

DAC8222FS

INL

GFSE

(LSB) (LSB)

1/2

Temperature

Range

–40°C to +85°C

0°C to +70°C

–55°C to +125°C

–40°C to +85°C

Package

Description

Cerdip-24

P-DIP-24

LCC-28

Cerdip-24

P-DIP-24

SOL-24

Package

Option

Q-24

N-24

E-28A

Q-24

N-24

R-24

*Consult factory for DAC8222/883 MIL-STD data sheet.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the DAC8222 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. C

–3–

DAC8222

DICE CHARACTERISTICS

11.

12.

13.

14.

15.

16.

17.

18.

19.

10.

11.

12.

AGND

OUT A

FB A

REF A

DGND

DB11(MSB)

DB10

DB9

DB8

DB7

DB6

DB5

13.

14.

15.

16.

17.

18.

19.

20.

21.

22.

23.

24.

DB4

DB3

DB2

DB1

DB0 (LSB)

DAC A/DAC

LDAC

REF B

FB B

OUT B

Substrate (die backside) is internally connected to V

DIE SIZE 0.124

0.132 inch, 16,368 sq. mils

(3.15

3.55 mm, 10.56 sq. mm)

WAFER TEST LIMITS

(@ V

Parameter

Relative Accuracy

Differential Nonlinearity

Full Scale Gain Error

Output Leakage

OUT A

, I

OUT B

)

Input Resistance

REF A

, V

REF B

)

Input Resistance Match

Digital Input High

Digital Input Low

Digital Input Current

Supply Current

DC Supply Rejection

(∆Gain/∆V

)

= +5 V or +15 V, V

REF A

= V

REF B

= +10 V, V

OUT A

= V

OUT B

= 0 V; AGND = DGND = 0 V; T

= +25 C)

Conditions

Endpoint Linearity Error

All Grades are Guaranteed Monotonic

Digital Inputs = 1111 1111 1111

Digital Inputs = 0000 0000 0000

Pads 2 and 24

Pads 4 and 22

DAC8222G

Limit

8/15

2.4

13.5

0.8

1.5

0.1

0.002

Units

LSB max

nA max

Symbol

INL

DNL

FSE

LKG

REF

∆R

REF

INH

INL

PSR

kΩ max

% max

V min

V max

V min

µA

max

mA max

%/% max

= +5 V

= +15 V

= +5 V

= +15 V

= 0 V or V

; V

INL

or V

INH

All Digital Inputs V

INL

or V

INH

All Digital Inputs 0 V or V

∆V

NOTES

Measured using internal R

FB A

and R

FB B

Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed

for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.

–4–

REV. C

DAC8222

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 1. Channel-to-Channel Match-

ing (DAC A and B are Superimposed)

Figure 2. Differential Nonlinearity

vs. V

REF

Figure 3. Differential Nonlinearity

vs. V

REF

Figure 4. Nonlinearity vs. V

REF

Figure 5. Nonlinearity vs. V

REF

Figure 6. Nonlinearity vs. V

Figure 7. Nonlinearity vs. Code

(DAC A and B are Superimposed)

Figure 8. Nonlinearity vs. Code at T

= –55

C, +25

C, +125

C for DAC A and

B (All Superimposed)

Figure 9. Absolute Gain Error

Changes vs. V

REF

REV. C

–5–

参数对比

与DAC8222FW相近的元器件有：DAC8222BTC/883、DAC8222FP、DAC8222、DAC8222EW、DAC8222FS、DAC8222GP。描述及对比如下：

型号	DAC8222FW	DAC8222BTC/883	DAC8222FP	DAC8222	DAC8222EW	DAC8222FS	DAC8222GP
描述	Dual 12-Bit Double-Buffered Multiplying CMOS D/A Converter	Dual 12-Bit Double-Buffered Multiplying CMOS D/A Converter	Dual 12-Bit Double-Buffered Multiplying CMOS D/A Converter	Dual 12-Bit Double-Buffered Multiplying CMOS D/A Converter	Dual 12-Bit Double-Buffered Multiplying CMOS D/A Converter	Dual 12-Bit Double-Buffered Multiplying CMOS D/A Converter	Dual 12-Bit Double-Buffered Multiplying CMOS D/A Converter
是否Rohs认证	不符合	不符合	不符合	-	不符合	不符合	不符合
厂商名称	ADI(亚德诺半导体)	ADI(亚德诺半导体)	ADI(亚德诺半导体)	-	ADI(亚德诺半导体)	ADI(亚德诺半导体)	ADI(亚德诺半导体)
零件包装代码	DIP	QLCC	DIP	-	DIP	SOIC	DIP
包装说明	DIP-24	LCC-28	DIP-24	-	DIP-24	SOL-24	DIP-24
针数	24	28	24	-	24	24	24
Reach Compliance Code	unknown	unknown	not_compliant	-	unknown	not_compliant	not_compliant
最大模拟输出电压	15 V	15 V	15 V	-	15 V	15 V	15 V
转换器类型	D/A CONVERTER	D/A CONVERTER	D/A CONVERTER	-	D/A CONVERTER	D/A CONVERTER	D/A CONVERTER
输入位码	BINARY, OFFSET BINARY	BINARY, OFFSET BINARY	BINARY, OFFSET BINARY	-	BINARY, OFFSET BINARY	BINARY, OFFSET BINARY	BINARY, OFFSET BINARY
输入格式	PARALLEL, WORD	PARALLEL, WORD	PARALLEL, WORD	-	PARALLEL, WORD	PARALLEL, WORD	PARALLEL, WORD
JESD-30 代码	R-GDIP-T24	S-CQCC-N28	R-PDIP-T24	-	R-GDIP-T24	R-PDSO-G24	R-PDIP-T24
JESD-609代码	e0	e0	e0	-	e0	e0	e0
最大线性误差 (EL)	0.0244%	0.0244%	0.0244%	-	0.0122%	0.0244%	0.0122%
位数	12	12	12	-	12	12	12
功能数量	1	1	1	-	1	1	1
端子数量	24	28	24	-	24	24	24
最高工作温度	85 °C	125 °C	85 °C	-	85 °C	85 °C	70 °C
最低工作温度	-40 °C	-55 °C	-40 °C	-	-40 °C	-40 °C	-
封装主体材料	CERAMIC, GLASS-SEALED	CERAMIC, METAL-SEALED COFIRED	PLASTIC/EPOXY	-	CERAMIC, GLASS-SEALED	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	DIP	QCCN	DIP	-	DIP	SOP	DIP
封装等效代码	DIP24,.3	LCC28,.45SQ	DIP24,.3	-	DIP24,.3	SOP24,.4	DIP24,.3
封装形状	RECTANGULAR	SQUARE	RECTANGULAR	-	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	IN-LINE	CHIP CARRIER	IN-LINE	-	IN-LINE	SMALL OUTLINE	IN-LINE
峰值回流温度（摄氏度）	NOT SPECIFIED	NOT SPECIFIED	NOT APPLICABLE	-	NOT SPECIFIED	240	NOT APPLICABLE
电源	5/15 V	5/15 V	5/15 V	-	5/15 V	5/15 V	5/15 V
认证状态	Not Qualified	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified
座面最大高度	5.08 mm	2.54 mm	5.33 mm	-	5.08 mm	2.65 mm	5.33 mm
最大稳定时间	1 µs	1 µs	1 µs	-	1 µs	1 µs	1 µs
最大压摆率	2 mA	2 mA	2 mA	-	2 mA	2 mA	2 mA
标称供电电压	5 V	5 V	5 V	-	5 V	5 V	5 V
表面贴装	NO	YES	NO	-	NO	YES	NO
技术	CMOS	CMOS	CMOS	-	CMOS	CMOS	CMOS
温度等级	INDUSTRIAL	MILITARY	INDUSTRIAL	-	INDUSTRIAL	INDUSTRIAL	COMMERCIAL
端子面层	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn85Pb15)	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)
端子形式	THROUGH-HOLE	NO LEAD	THROUGH-HOLE	-	THROUGH-HOLE	GULL WING	THROUGH-HOLE
端子节距	2.54 mm	1.27 mm	2.54 mm	-	2.54 mm	1.27 mm	2.54 mm
端子位置	DUAL	QUAD	DUAL	-	DUAL	DUAL	DUAL
处于峰值回流温度下的最长时间	NOT SPECIFIED	NOT SPECIFIED	NOT APPLICABLE	-	NOT SPECIFIED	30	NOT APPLICABLE
宽度	7.62 mm	11.43 mm	7.62 mm	-	7.62 mm	7.5 mm	7.62 mm
Base Number Matches	1	1	1	-	1	1	1
长度	-	11.43 mm	30.48 mm	-	-	15.4 mm	30.48 mm