DEMO MANUAL DC1783A
LTC2380/LTC2379/LTC2378/
LTC2377/LTC2376: 18-Bit/16-Bit, 2Msps/1.6Msps/1Msps/
500ksps/250ksps Low Power, Low Noise ADCs
DESCRIPTION
The
LTC2380/LTC2379/LTC2378/LTC2377/LTC2376
are
low power, low noise ADCs with serial outputs that can
operate from a single 2.5V supply. The following text refers
to the LTC2379-18 but applies to all parts in the family,
the only difference being the maximum sample rates and
the number of bits. The LTC2379-18 supports a ±5V fully
differential input range with a 101dB SNR, consumes
only 18mW and achieves ±2LSB INL max with no miss-
ing codes at 18-bits. The
DC1783A
demonstrates the DC
and AC performance of the LTC2379-18 in conjunction
with the DC590 QuikEval™ and DC718 PScope™ data
collection boards. Use the DC590 to demonstrate DC
performance such as peak-to-peak noise and DC linearity.
Use the DC718 if precise sampling rates are required or to
demonstrate AC performance such as SNR, THD, SINAD
and SFDR. The demonstration circuit 1783A is intended
to demonstrate recommended grounding, component
placement and selection, routing and bypassing for this
ADC. Several suggested driver circuits for the analog
inputs will be presented.
Design files for this circuit board are available at
http://www.linear.com/demo
L,
LT, LTC, LTM, µModule, Linear Technology and the Linear logo are registered trademarks
and QuikEval and PScope are trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
–9V
GND
+9V
CLK IN
100MHz MAX
3.3V
P-P
MAX
A
IN
+
0V TO V
REF
MAX
TO DC718
A
IN
–
0V TO V
REF
MAX
TO DC590
DC1783A F01
Figure 1. DC1783A Connection Diagram
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DEMO MANUAL DC1783A
DESCRIPTION
Table 1. DC1783A Assembly Options
ASSEMBLY VERSION
DC1783A-A
DC1783A-B
DC1783A-C
DC1783A-D
DC1783A-E
DC1783A-F
DC1783A-G
DC1783A-H
U1 PART NUMBER
LTC2380CMS-16
LTC2378CMS-16
LTC2377CMS-16
LTC2376CMS-16
LTC2379CMS-18
LTC2378CMS-18
LTC2377CMS-18
LTC2376CMS-18
MAX CONVERSION RATE
2Msps
1Msps
500ksps
250ksps
1.6Msps
1Msps
500ksps
250ksps
NUMBER OF BITS
16
16
16
16
18
18
18
18
MAX CLK IN FREQUENCY
100MHz
50MHz
25MHz
12.5MHz
99.2MHz
62MHz
31MHz
15.5MHz
QUICK START PROCEDURE
DC718
Check to make sure that all switches and jumpers are
set as shown in the connection diagram of Figure 1. The
default connections configure the ADC to use the onboard
reference and regulators to generate the required common
mode voltages. The analog input is DC-coupled. Connect
the DC1783A to a DC718 USB High Speed Data Collection
Board using connector J2. Then, connect the DC718 to a
host PC with a standard USB A/B cable. Apply ±9V to the
indicated terminals. Then apply a low jitter signal source
to J4. The default setup uses a single-ended to differential
converter so that it is only necessary to apply a single-ended
input signal to J4. Connect a low jitter 100MHz 3.3V
P-P
sine wave or square wave to connector J1. Note that J1
has a 50Ω termination resistor to ground.
Run the PScope software (PScope.exe version K72 or
later) supplied with the DC718 or download it from www.
linear.com.
Complete software documentation is available from the
Help menu. Updates can be downloaded from the Tools
menu. Check for updates periodically as new features
may be added.
The PScope software should recognize the DC1783A and
configure itself automatically.
Click the COLLECT button (See Figure 6) to begin acquiring
data. The Collect button then changes to Pause, which can
be clicked to stop data acquisition.
DC590 SETUP
IMPORTANT! To avoid damage to the DC1783A, make
sure that V
CCIO
(JP6) is set to 3.3V before connecting the
DC590 to the DC1783A.
To use the DC590 with the DC1783A, it is necessary to
apply –9V and ground to the –9V and GND terminals or
disable amplifier U15 by moving R32 and R36 to R31 and
R38 respectively. If U15 is disabled, it is required that J4
and J8 are both driven. If U15 is not disabled then it is
only necessary to drive J4. Connect the DC590 to a host
PC with a standard USB A/B cable. Connect the DC1783A
to a DC590 USB serial controller using the supplied
14-conductor ribbon cable. Apply a signal source to J4 or
J4 and J8 depending on how the DC1783A is configured.
Run the evaluation software supplied with the DC590 or
download it from www.linear.com. The correct control
panel will be loaded automatically. Click the COLLECT
button (Figure 7) to begin reading the ADC.
DC1783A SETUP
DC Power
The DC1783A requires ±9VDC and draws 100mA. Most
of the supply current is consumed by the CPLD, opamps,
regulators and discrete logic on the board. The 9VDC
input voltage powers the ADC through LT1763 regulators
which provide protection against accidental reverse bias.
Additional regulators provide power for the CPLD and
opamps. See Figure 1 for connection details.
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DEMO MANUAL DC1783A
QUICK START PROCEDURE
Clock Source
You must provide a low jitter 3.3V
P-P
sine or square wave
to J1. The clock input is AC-coupled so the DC level of the
clock signal is not important. A generator like the HP8644
or the DC1216A-A is recommended. Even a good generator
can start to produce noticeable jitter at low frequencies.
Therefore it is recommended for lower sample rates to
divide down a higher frequency clock to the desired sample
rate. The ratio of clock frequency to conversion rate is
62:1 for 18-bit parts and 50:1 for 16-bit parts. If the clock
input is to be driven with logic, it is recommended that the
50Ω terminator (R5) be removed. Slow rising edges may
compromise the SNR of the converter in the presence of
high-amplitude higher frequency input signals.
Data Output
Parallel data output from this board (0V to 3.3V default),
if not connected to the DC718, can be acquired by a logic
analyzer, and subsequently imported into a spreadsheet, or
mathematical package depending on what form of digital
signal processing is desired. Alternatively, the data can be
fed directly into an application circuit. Use pin 3 of J2 to
latch the data. The data can be latched using either edge
of this signal. The data output signal levels at J2 can also
be reduced to 0V to 2.5V if the application circuit cannot
tolerate the higher voltage. This is accomplished by mov-
ing JP3 to the 2.5V position.
Reference
The default reference is a LTC6655 5V reference. Alterna-
tively, if a lower power reference is desired, this reference
(U20) can be removed and a LTC6652 5V reference can
be installed in the U10 position. This will result in only
a small loss in performance in applications where the
ADC is continuously converting. If an external reference
is used it must settle quickly in the presence of glitches
on the REF pin.
Analog Input
The default driver for the analog inputs of the LTC2379-18
on the DC1783A is shown in Figure 2. This circuit converts
a single-ended 0V to 5V input signal applied at A
IN+
into
a differential signal with a swing of ±5V between the +IN
and –IN inputs of the ADC. In addition, this circuit band
limits the input frequencies to approximately 800kHz.
C39
0.003µF R16
0
NPO
C19
0.003µF
NPO
R36
20
C40
R19
0.003µF 0
NPO
A
IN
0V TO V
REF
LT6350
V
REF
/2
C45
10µF
R32
20
+
LTC2379-18
–
DC1783A F02
Figure 2. Single-Ended to Differential Converter
Alternatively, if your application circuit produces a differ-
ential signal which can drive the ADC but you need to level
shift the input signal, the circuit shown in Figure 3 can be
used. The circuit in Figure 3 AC-couples the input signal
and is usable down to about 10kHz. The lower frequency
limit can be extended by increasing C17 and C48.
AC-coupling the input may degrade the distortion per-
formance of the ADC due to nonlinearity of the coupling
capacitor (C17). The circuit in Figure 3 can be implemented
on the DC1783A by putting JP1 and JP5 in the AC posi-
tion, moving R32 and R36 to the R31 and R38 positions
and adding a 1k resistor at the R9 location. At this point
it will be necessary to drive both A
IN+
and A
IN–
. One of
these RC pairs can be attached to the input of the circuit
in Figure 2. This allows a single-ended input signal to be
level shifted.
One of the most asked for ADC driver circuits is one that
allows the input voltage to swing below ground while using
a single supply ADC. The input driver shown in Figure 4
accepts a true bipolar input voltage range of ±10V and
converts it to the 0V to 5V input swing of the ADC. The
circuit of Figure 4 can be implemented on the DC1783A
by replacing R9 with 499Ω, R15 with 2k, R35 with 2k and
R45 with 499Ω.
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DEMO MANUAL DC1783A
QUICK START PROCEDURE
Data Collection
For SINAD, THD or SNR testing a low noise, low distortion
generator such as the B&K Type 1051 or Stanford Research
DS360 should be used. A low jitter RF oscillator such as
the HP8644 or DC1216A-A is used as the clock source.
This demo board is tested in house by attempting to
duplicate the FFT plot shown on the front page of the
LTC2379-18 data sheet. This involves using a 100MHz clock
source, along with a sinusoidal generator at a frequency of
2kHz. The input signal level is approximately –1dBFS. The
input is level shifted and filtered with the circuit shown in
Figure 5. A typical FFT obtained with DC1783A is shown
in Figure 6. Note that to calculate the real SNR, the signal
level (F1 amplitude = –1.080dB) has to be added back to
the SNR that PScope displays. With the example shown in
Figure 6 this means that the actual SNR would be 101.07dB
instead of the 99.99dB that PScope displays. Taking the
RMS sum of the recalculated SNR and the THD yields
a SINAD of 100.7dB which is fairly close to the typical
number for this ADC.
There are a number of scenarios that can produce mis-
leading results when evaluating an ADC. One that is
common is feeding the converter with a frequency, that
V
CM
C17
10µF
R9
1k
R31
20
C39
0.003µF R16
0
NPO
C19
0.003µF
NPO
C48
10µF
R40 R38
1k 20
V
CM
C40
R19
0.003µF 0
NPO
10V TO –10V
A
IN
V
CM
R9
499Ω
R15
2k
1
LT6350
8
4
0V TO 5V
TO IN
+
+
–
2
–
+
5
DC1783A F04
5V TO 0V
TO IN
–
R35
2k
R45
499Ω
+
–
V
CM
= V
REF
/2
Figure 4. ±10V Single-Ended to 0V to 5V Differential
DC-Coupled Driver
V
REF
1k
SINE IN
–V
REF
TO +V
REF
1k
A
IN+
0.15µF
DC1783A F05
Figure 5. Level Shift and Filter Circuit Used for Board Testing
A
IN+
0V TO V
REF
A
IN–
0V TO V
REF
+IN
–IN
DC1783A F03
Figure 3. AC-Coupled Differential Driver
is a sub-multiple of the sample rate, and which will only
exercise a small subset of the possible output codes. The
proper method is to pick an M/N frequency for the input
sine wave frequency. N is the number of samples in the
FFT. M is a prime number between one and N/2. Multiply
M/N by the sample rate to obtain the input sine wave
frequency. Another scenario that can yield poor results
is if you do not have a signal generator capable of ppm
frequency accuracy or if it cannot be locked to the clock
frequency. You can use an FFT with windowing to reduce
the leakage or spreading of the fundamental, to get a close
approximation of the ADC performance. If an amplifier or
clock source with poor phase noise is used, the windowing
will not improve the SNR.
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DEMO MANUAL DC1783A
QUICK START PROCEDURE
Layout
As with any high performance ADC, this part is sensitive
to layout. The area immediately surrounding the ADC on
the DC1783A should be used as a guideline for place-
ment, and routing of the various components associated
with the ADC. Here are some things to remember when
laying out a board for the LTC2379-18. A ground plane is
necessary to obtain maximum performance. Keep bypass
capacitors as close to supply pins as possible. Use indi-
vidual low impedance returns for all bypass capacitors.
Use of a symmetrical layout around the analog inputs will
minimize the effects of parasitic elements. Shield analog
input traces with ground to minimize coupling from other
traces. Keep traces as short as possible.
Component Selection
When driving a low noise, low distortion ADC such as
the LTC2379-18, component selection is important so
as to not degrade performance. Resistors should have
low values to minimize noise and distortion. Metal film
resistors are recommended to reduce distortion caused
by self heating. Because of their low voltage coefficients,
to further reduce distortion NPO or silver mica capacitors
should be used. Any buffer used to drive the LTC2379-18
should have low distortion, low noise and a fast settling
time such as the LT6350.
DC1783A JUMPERS
Definitions
JP1:
Selects AC- or DC-coupling of A
IN+
. The default set-
ting is DC.
JP2:
V
CM
sets the DC bias for A
IN+
and A
IN–
when the
inputs are AC-coupled. V
REF
/2 is the default setting.
JP3:
V
CCIO
sets the output levels at J2 to either 3.3V or
2.5V. Use 3.3V to interface to the DC718 which is the
default setting.
JP5:
Selects AC- or DC-coupling of A
IN–
. The default set-
ting is DC.
JP6:
FS selects whether the digital gain compression is
on or off. In the V
REF
position digital gain compression
is off and the analog input range at A
IN+
is 0V to V
REF
. In
the 0.8V
REF
position digital gain compression is turned on
and the analog input range at A
IN+
is 0.1V
REF
to 0.9V
REF
.
JP7:
Selects –3.6V or ground for V
–
. The default is –3.6V.
Setting JP7 to ground is useful for evaluating single sup-
ply operation of the buffer when operating the ADC with
digital gain compression turned on.
JP8:
Selects 8V or 5V for V
+
. The default is 8V. Setting JP8
to 5V is useful for evaluating single 5V supply operation
of the buffer when operating the ADC with digital gain
compression turned on.
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