Device
Engineering
Incorporated
385 East Alamo Drive
Chandler, AZ 85225
Phone: (480) 303-0822
Fax: (480) 303-0824
E-mail: admin@deiaz.com
DEI1041
ARINC 429 LINE RECEIVER
FEATURES
ARINC 429 to TTL/CMOS logic line receiver
Operates from single +5V ± 10% or 3.3V ± 10% power supply
ARINC inputs internally protected to lightning requirements of DO-160D Level A3
Operates in high noise environment
o
Input Common Voltage Range: ± 20V
o
2V minimum Input hysteresis
Logic level TEST inputs bypass analog inputs.
8 Lead SOIC.
Replacement for HI-8588 and HI-8588-10
TERMINAL DESCRIPTION
Table 1 Terminal Description
NAME
INA
DESCRIPTION
429 INPUT.
ARINC 429 format serial digital data
“A” input.
429 INPUT.
ARINC 429 format serial digital data
“B” input.
LOGIC INPUT.
Test input A.
LOGIC INPUT.
Test input B.
LOGIC OUTPUT.
CMOS/TTL format serial digital
data “A” output.
LOGIC OUTPUT.
CMOS/TTL format serial digital
data “B” output.
POWER INPUT.
5 VDC OR 3.3VDC.
POWER INPUT.
Ground.
INB
TESTA
TESTB
OUTA
OUTB
VDD
GND
©2014 Device Engineering Inc.
Page 1 of 8
DS-MW-01041-01 Rev L
04/29/2014
FUNCTIONAL DESCRIPTION
The DEI1041 is a BICMOS device which contains one ARINC 429 differential line receiver. It translates incoming ARINC
429 data bus signals (tri-level RZ bipolar differential modulation) to a pair of TTL/CMOS logic outputs. It meets the
requirements of the ARINC 429 Digital Information Transfer Standard. Refer to Figure 1 “ DEI1041 Block Diagram and
Truth Table”.
The device is designed to operate in a high noise environment. Inputs are accepted over a +/- 20V common mode voltage
range and the receivers provide over 2 Volts of hysteresis. Circuit speed is optimized to reject high frequency transients.
All ARINC input pins are designed with internal protection from damage due to transients meeting the lightning induced
transient requirements of DO-160D Level A3. The ARINC inputs may optionally be connected to ARINC bus through
external 10k ohm series resistors. These resistors may be added in combination with transient voltage suppressors to achieve
lighting protection beyond the Level A3 limits due to high input impedance.
The DEI1041 device provides logic level TEST inputs for built in system test. They force the receiver outputs to the specified
ZERO, ONE or NULL state. The ARINC inputs are ignored when the device is in test mode.
DEI1041 Block Diagram
Typical Channel
DEI1041 Truth Table
INPUTS
TEST INPUTS
(TTL/CMOS)
ARINC
INPUTS
OUTPUTS
TTL/CMOS
INA
OUTA
RESISTOR
NETWORK
AND
LIGHTNING
PROTECTION
TEST A TEST B A
IN
– B
IN
V
OUTPUT
AND
TEST
LOGIC
Comparators
OUT A OUT B Logic
1
0
0
0
1
0
0
1
0
1
0
0
ONE
ZERO
NULL
ZERO
ONE
NULL
INB
0
OUTB
0
0
0
1
0
1
>6.5v
<-6.5V
-2.5 to +2.5
X
X
X
0
0
0
1
1
TESTA
IINPUT
BUFFERS
TESTB
Figure 1 DEI1041 Block Diagram and Truth Table
ELECTRICAL DESCRIPTION
Table 2 Recommended Operating Conditions
PARAMETER
Supply Voltage
Logic Input Levels
Operating Temperature
-SES
-SMS
SYMBOL
Vdd
V
TESTA,B
Ta
CONDITIONS
+5V ± 10%
+3.3V ± 10%
0 to Vdd
-55 to +85°C
-55 to +125°C
©2014 Device Engineering Inc.
Page 2 of 8
DS-MW-01041-01 Rev L
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Table 3 Absolute Maximum Rating
PARAMETER
Supply Voltage (with respect to V
SS
)
Storage Temperature
Input Voltage, continuous (ARINC Inputs)
Input Voltage (Test Inputs)
Power Dissipation @ 85 °C
Junction Temperature:
Tjmax, (limited by molding compound Tg)
Peak Body Temperature,
- G Package
Lightning Protection (ARINC 429 Channel Inputs and TESTA/TESTB Inputs)
Waveform 3 (2)
Waveform 4, 5A, 5B* (2) (3)
ESD per JEDEC A114-A Human Body Model
Notes:
-600
-300
-1000
MIN
-0.3
-65
-40
V
SS
– 0.3
MAX
7.0
+150
+40
V
DD
+0.3
500
145
260
+600
+300
1000
UNITS
V
°C
V
V
mW
°C
o
C
V
V
V
1.
2.
3.
Stresses above these limits can cause permanent damage.
Per DO160D, Sect 22 Level 3A. See Figures 4-6.
Inputs can be protected to withstand higher stress by adding series resistors and shunt TVS on inputs. Inputs
withstand 1500V Waveform 5A when clipped 600V.
Table 4 Electrical Characteristics
Conditions:
Temperature: -55°C to +85°C (SES) : -55°C to +125°C (SMS); V
DD
= +5V ± 10% or 3.3V ± 10%
PARAMETER
V
A
– V
B
= Logic +1
V
A
– V
B
= Logic -1
V
A
– V
B
= Logic Null
Input Hysteresis
V
A
– V
B
= Null to +1 transition
V
A
– V
B
= +1 to Null transition
V
A
– V
B
= Null to -1 transition
V
A
– V
B
= -1 to Null transition
Input Common Mode
Voltage Range
Input Resistance
IN
A
to IN
B
Input Resistance
IN
A
or IN
B
to V
SS
Input Capacitance
IN
A
to IN
B
OUTA = 0 1
OUTA = 1 0
OUTB = 0 1
OUTB = 1 0
Logic +1, Null, Logic -1
V
DD
open,
Shorted to V
SS
or +5V (1)
V
DD
open,
Shorted to V
SS
or +5V
V
DD
open,
Shorted to V
SS
or +5V (1)
TEST CONDITION
SYMBOL
MIN
6.5
-6.5
-2.5
2.0
5.5
2.5
-6.5
-3.5
-20
280k
140k
780K
390K
10
pF
NOM
10
-10
0
MAX
13
-13
2.5
UNITS
V
V
V
V
V
V
V
V
V
ARINC INPUTS
OUTA = 1
V
+1
OUTB = 1
OUTA = 0
OUTB = 0
V
-1
V
NULL
V
HY
V
T+1+
V
T+1-
V
T-1+
V
T-1-
V
CM
R
IN
R
S
C
IN
4.0
6.5
3.5
-5.5
-2.5
+20
©2014 Device Engineering Inc.
Page 3 of 8
DS-MW-01041-01 Rev L
04/29/2014
Conditions:
Temperature: -55°C to +85°C (SES) : -55°C to +125°C (SMS); V
DD
= +5V ± 10% or 3.3V ± 10%
PARAMETER
Input Capacitance
IN
A
or IN
B
to V
SS
TEST CONDITION
V
DD
open,
Shorted to V
SS
or +5V (1)
SYMBOL
C
S
MIN
NOM
MAX
10
UNITS
pF
TEST INPUTS
Logic 0 Voltage
Logic 1 Voltage
Logic 0 Current
Logic 1 Current
V
IL
= 0.8
V
IL
V
IH
I
IL
V
IH
= 2.0
I
IH
LOGIC OUTPUTS
I
OH
= 5mA (VDD=5V)
I
OH
= 1.5mA (VDD=3.3V)
V
OH
TTL Compatible
I
OL
= 5mA (VDD=5V)
V
OL
I
OL
= 1.5mA (VDD=3.3V)
TTL Compatible
I
OH
= 100µA
V
OH
CMOS Compatible
I
OL
= 100µA
V
OH
CMOS Compatible
SUPPLY CURRENT
Data Rate = 0MHz,
A/BIN =open,
I
DD
A/BOUT=open,
Vdd = 5.5V or 3.63V
2.0
20
20
0.8
V
V
µA
µA
OUT A or OUT B
2.4
0.5
0.4
V
DD
–
50mV
V
SS
+
50mV
V
OUT A or OUT B
OUT A or OUT B
OUT A or OUT B
V
V
V
V
DD
Current
Notes:
1.
2.
2.5
5
mA
Guaranteed by design, not production tested.
Current flowing into device is positive. Current flowing out of device is negative. All voltages are with respect
to Ground unless otherwise noted.
Table 5 Switching Characteristics
PARAMETER
TEST CONDITION
TESTA = TESTB = 0
C
L
= 50pF
TESTA = TESTB = 0
C
L
= 50pF
10% to 90%, C
L
= 50pF
10% to 90%, C
L
= 50pF
C
L
= 50pF
C
L
= 50pF
SYMBOL
MAX
MAX
UNITS
Vdd 3.3V Vdd 5V
INA/B to OUT A/B Prop Delay
INA/B to OUT A/B Prop Delay
Matching of t
LH
and t
HL
OUT A/B rise time
OUT A/B fall time
TESTA/B to OUTA/B Prop
delay
TESTA/B to OUTA/B Prop
delay
t
LH
t
HL
Dtp
t
r
t
f
t
TOH
t
TOL
1000
1000
500
50
50
100
100
900
900
500
25
25
60
60
ns
ns
ns
ns
ns
ns
ns
©2014 Device Engineering Inc.
Page 4 of 8
DS-MW-01041-01 Rev L
04/29/2014
V/I
INA
Vdif = 6.5V
Largest
Peak
Vdif = 2.5V
25% to 75%
of Largest Peak
50%
INB
t
HL
t
LH
0
t
OUTA
OUTB
1.5V
1.5V
Figure 2 ARINC 429 Input to Logic Output Switching
Waveform
Figure 4 DO160D Lightning Induced Transient
Voltage Waveform #3.
Voc = 600V, Isc = 24A, Frequency =1MHz +-20%
V
Peak
TESTA OR B
1.5V
t
TOH
T1 = 6.4 us +-20%
T2 = 70us +-20%
t
TOL
50%
OUTA OR B
1.5V
0
T1
t
T2
Figure 3 TEST Input to Logic Output Switching
Waveform
Figure 5 DO160D Lightning Induced Transient
Voltage Waveform #4.
Voc = 300V, Isc = 60A
V/I
LIGHTNING TRANSIENT NOTES:
1. Voc = Peak Open Circuit Voltage available at the
calibration point.
2. Isc = Peak Short Circuit Current available at the
calibration point.
3. Amplitude tolerances: +10%, -0%.
4. The ratio of Voc to Isc is the generator source
impedance to be used for generating the
waveforms.
Peak
5A: T1 = 40us +-20%
T2 = 120us +-20%
5B: T1 = 50us +-20%
T2 = 500us +-20%
50%
0
Figure 6 DO160D Lightning Induced Transient
t
Voltage Waveform #5.
T1
T2
Voc = 300V, Isc = 300A
©2014 Device Engineering Inc.
Page 5 of 8
DS-MW-01041-01 Rev L
04/29/2014
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