DFXO
LVDS - LVPECL & CMOS Output
20 MHz to 300 MHz
Differential Output Crystal Oscillator
DESCRIPTION
5mm x 7mm
Statek’s 5 mm x 7 mm surface mount Differential Output
Crystal Oscillator is designed for applications requiring low jitter
and ultra high frequency differential outputs in a small footprint.
Offered at frequencies from 20 MHz to 300 MHz with operation
over a temperature range of (-40°C to +105°C). No external
decoupling capacitor required with internal capacitor.
FEATURES
Low Profile
DIMENSIONS
LVDS - LVPECL- CMOS outputs available
Low phase noise - Low phase jitter
Internal 0.01µF SMD decoupling capacitor
Low Allan deviation
High Frequency Fundamental Mode Crystal
Extended Industrial temperature range
APPLICATIONS
PACKAGE DIMENSIONS
Dimension
A
B
C
(SM1)
C
(SM3/SM5)
D
E
Military & Aerospace
Avionics
Communications
Networking
TERMINATIONS
Minimum
mm
6.86
4.85
1.55
1.65
1.19
1.07
Typical
mm
7.00
5.00
1.75
1.85
1.40
1.27
Maximum
mm
7.16
5.16
1.95
2.05
1.41
1.47
Designation
SM1
SM3
SM5
Termination
Gold Plated (Pb Free)
Solder Dipped
Solder Dipped (Pb Free
)
SUGGESTED LAND PATTERN
0.100
(2.54)
0.077
(1.96)
inches
(mm)
ENABLE/DISABLE OPTIONS (T/N)
Statek offers two enable/disable options: T and N. The T-version
has a Tri-State output and continues to oscillate internally when the
output is put into the high Z state. As a result, when re-enabled,
the oscillator does not have to restart and an output with a stable
frequency resumes almost immediately. The N-version does not
have PIN 2 connected internally and so has no enable/disable
capability. The following table describes the Enable/Disable option T.
ENABLE/DISABLE OPTION T FUNCTION TABLE
0.144
(3.65)
0.070
(1.80)
0.200
(5.08)
PIN CONNECTIONS
Enable (PIN 1 High*)
Output
Oscillator
Current
Frequency Output
Oscillates
Normal
Disable (PIN 1 Low)
High Z State
Oscillates
Lower than normal
*
When PIN 1 is allowed to float, it is held high by an internal pull-up resistor.
1.
2.
3.
4.
5.
6.
(T) Enable/Disable or not connected (N)
(NC) Not Connected
Ground
LVDS - LVPECL - CMOS
LVDS - LVPECL (complementary)
Supply Voltage (V
DD
)
10196 Rev C
STATEK CORPORATION 512 N. MAIN ST., ORANGE, CA 92868 714-639-7810 FAX: 714-997-1256
www.statek.com
ABSOLUTE MAXIMUM RATINGS
SPECIFICATIONS
Supply Voltage V
DD
-0.5 V to 4.6 V
Storage Temperature
-65
O
C to +150
O
C
Maximum Process Temperature
260
O
C for 10 seconds
ESD Protection Human Body Model 2kV
PACKAGING OPTIONS
Nominal Frequency
Operating Temperature
Supply Voltage
2
1
20 MHz to 300 MHz
-40
O
C to +85
O
C
3.3V
±
10%
(2.5 V ±10% Available)
DFXO - Tray Pack
- Tape and reel Per EIA 481
SPECIFICATIONS TABLE
Parameter
Frequency Stability
3
Shock, survival
Vibration, survival
6
5,000 g, 0.3 ms, ½ sine
20 g, 10-2,000 Hz swept sine
Parameters listed are at 25°C unless otherwise noted.
Units
PPM
PPM
PPM
PPM
PPM
Tightest
±75
±25
±25
±25
Standard
±100
±50
±5
±50
±50
Maximum
±150
±100
±100
±100
Conditions / Comments
-40°C to +105°C
-40°C to +85°C
First year depending on frequency
@25°C Other tolerances available
-40°C to +85ºC
Symbol
Aging
4
Calibration Tolerance
Frequency Tolerance (Total)
LVDS Output
Parameter
Symbol
Output Differential Voltage
V
OD
V
DD
Magnitude Change
Δ
V
OD
Output High Voltage
V
OH
Output Low Voltage
V
OL
Offset Voltage
V
OS
Offset Magnitude Change
Δ
V
OS
Power-off Leakage
I
OXD
Short Circuit Current (Output)
I
OSD
Rise Time (Differential Clock)
t
R
Fall Time (Differential Clock)
t
F
Supply Current
(Outputs Loaded)
I
DD
5
Duty Cycle (Output Clock)
LVPECL Output
Parameter
Symbol
Output High Voltage
Output Low Voltage
Rise Time
t
R
Fall Time
t
F
Supply Current
(Outputs Loaded)
I
DD
5
Duty Cycle (Output Clock)
Units
mV
mV
V
V
V
mV
uA
mA
nS
nS
mA
%
Minimum
247
-50
0.9
1.125
0
Typical
355
1.4
1.1
1.2
3
±1
-6
0.7
0.7
30*
Maximum
454
50
1.6
1.375
25
±10
-8
1
1
80
60
Conditions / Comments
RL = 100
Ω
(See Figure 2)
V
OUT
=V
DD
or GND (V
DD
= 0V)
R
L
=100
Ω
20% to 80%
(See Figures 3 & 4)
* Typical for 125 MHz
@ 1.25 V
0.2
0.2
40
Units
Minimum
V
DD
-1.025
Typical
Maximum
Conditions / Comments
R
L
=50
Ω
to (V
DD
-2V)
(See Figure 5)
20% to 80% (See Figure 6)
20% to 80% (See Figure 6)
@
V
DD
-1.3V
nS
nS
mA
%
0.6
0.5
40
V
DD
-1.620
1.5
1.5
100
60
CMOS Output
Parameter
Symbol
Units
Short Circuit Current
mA
Output Drive Current
I
OH
mA
(CMOS)
I
OL
mA
Rise/Fall Time (CMOS)
trtf
nS
Output Load (CMOS)
CL
pF
Supply Current
(Outputs Loaded)
I
DD
mA
5
Duty Cycle (Output Clock)
%
Timing Jitter
Jitter (Integrated) (LVDS)
pS
Jitter (Period) (LVDS)
pS
Offset Frequency
Phase Noise - 125 MHz
Typical (LVDS)
L(f)
dBc/Hz
1.
2.
3.
4.
5.
6.
-40°C to +105°C at selected frequencies. Please contact factory.
2.5 V available for frequencies up to 160 MHz.
Does not include calibration tolerance.
Contact factory for tighter tolerance.
Contact factory for 45/55% duty cycle.
Per MIL-STD-202G, Method 204D, Random vibration testing also available.
Minimum
20
20
Typical
±50
25
25
1.5
Maximum
Conditions / Comments
40
0.3
2.0
@ 100 Hz
-110
15
40
60
0.4
@ 1 kHz
-133
V
OH
=V
DD
-0.4V,
V
DD
=3.3V
V
OL
=0.4V,
V
DD
=3.3V
10% to 90% 3.3V, 15pF
(See Figure 1)
200 MHz Maximum
@ 50%V
DD
125 MHz (12 kHz to 20 MHz RMS)
125 MHz (10,000 cycles RMS)
@ 10 kHz
@ 100 kHz
-143
-148
@ 10 Hz
-85
10196 Rev C
STATEK CORPORATION 512 N. MAIN ST., ORANGE, CA 92868 714-639-7810 FAX: 714-997-1256
www.statek.com
HOW TO ORDER DFXO SURFACE MOUNT CRYSTAL OSCILLATORS
DFXO
C
4
Supply Voltage
2 = 2.5 V
4 = 3.3 V
T
Enable/Disable
Option T or N
SM3
Terminations
Blank = SM1
= Gold Plated (Pb Free)
SM3 = Solder Dipped
SM5 = Solder Dipped (Pb Free)
300.0M
Frequency
M = MHz
,
50
Calibration
Tolerance
@ 25
O
C
(in ppm)
/
50
Frequency
Stability over
Temp. Range
(in ppm)
/
/
I
Output Type
C = CMOS
D = LVDS
P = LVPECL
OR
/
/
100
Total
Frequency
Tolerance
(in ppm)
Temperature Range
C = -10
O
C to +70
O
C
I
= -40
O
C to +85
O
C
E = -40
O
C to +105
O
C
S = Customer Specified
/
I
CMOS Test Circuit
Temperature Range
C = -10
O
C to +70
O
C
I
= -40
O
C to +85
O
C
E = -40
O
C to +105
O
C
S = Customer Specified
Note: a 0.1µF bypass capacitor between VDD and GND pins as close as
possible is recommended to minimize power supply line noise.
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
10196 Rev C
STATEK CORPORATION 512 N. MAIN ST., ORANGE, CA 92868 714-639-7810 FAX: 714-997-1256
www.statek.com
