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DLO32F-3MD1

SQUARE, 10.2 MHz, WAVEFORM GENERATION, PDIP5

器件类别:模拟混合信号IC    信号电路   

厂商名称:Data Delay Devices

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器件参数
参数名称
属性值
是否Rohs认证
不符合
厂商名称
Data Delay Devices
包装说明
DFP,
Reach Compliance Code
compli
ECCN代码
EAR99
模拟集成电路 - 其他类型
SQUARE
JESD-30 代码
S-XDFP-F14
功能数量
1
端子数量
14
最高工作温度
70 °C
最低工作温度
最大输出频率
3.06 GHz
封装主体材料
UNSPECIFIED
封装代码
DFP
封装形状
SQUARE
封装形式
FLATPACK
峰值回流温度(摄氏度)
NOT SPECIFIED
认证状态
Not Qualified
座面最大高度
5.715 mm
最大供电电压 (Vsup)
5.25 V
最小供电电压 (Vsup)
4.75 V
标称供电电压 (Vsup)
5 V
表面贴装
YES
温度等级
COMMERCIAL
端子形式
FLAT
端子节距
1.27 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
NOT SPECIFIED
文档预览
DLO32F
TTL-INTERFACED, GATED
DELAY LINE OSCILLATOR
(SERIES DLO32F)
FEATURES
Continuous or keyable wave train
Synchronizes with arbitrary gating signal
Fits standard 14-pin DIP socket
Low profile
Auto-insertable
Input & outputs fully TTL interfaced & buffered
Available in frequencies from 2MHz to 40MHz
C1
1
14
data
3
®
delay
devices,
inc.
PACKAGES
VCC
10
GND
7
8
C2
GB
C1
N/C
N/C
N/C
N/C
N/C
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
N/C
N/C
N/C
C2
N/C
GB
DLO32F-xx
DLO32F-xxA2
DLO32F-xxB2
DLO32F-xxM
DIP
Gull-Wing
J-Lead
Military DIP
Military SMD
DLO32F-xxMD1
DLO32F-xxMD4
FUNCTIONAL DESCRIPTION
The DLO32F-series device is a gated delay line oscillator. The device
produces a stable square wave which is synchronized with the falling edge
of the Gate Input (GB). The frequency of oscillation is given by the device
dash number (See Table). The two outputs (C1,C2) are in complementary
during oscillation, but both return to logic low when the device is disabled.
PIN DESCRIPTIONS
GB
C1
C2
VCC
GND
Gate Input
Clock Output 1
Clock Output 2
+5 Volts
Ground
SERIES SPECIFICATIONS
Frequency accuracy:
Inherent delay (T
E0
):
Output skew:
Output rise/fall time:
Supply voltage:
Supply current:
Operating temperature:
Temperature coefficient:
2%
3ns typical
2.5ns typical
2ns typical
5VDC
±
5%
40ma typical (7ma when disabled)
0° to 70° C
100 PPM/°C (See text)
DASH NUMBER
SPECIFICATIONS
Part
Number
DLO32F-2
DLO32F-2.5
DLO32F-3
DLO32F-3.5
DLO32F-4
DLO32F-4.5
DLO32F-5
DLO32F-5.5
DLO32F-6
DLO32F-7
DLO32F-8
DLO32F-9
DLO32F-10
DLO32F-12
DLO32F-14
DLO32F-15
DLO32F-20
DLO32F-25
DLO32F-30
DLO32F-35
DLO32F-40
Frequency
(MHz)
2.0
±
0.04
2.5
±
0.05
3.0
±
0.06
3.5
±
0.07
4.0
±
0.08
4.5
±
0.09
5.0
±
0.10
5.5
±
0.11
6.0
±
0.12
7.0
±
0.14
8.0
±
0.16
9.0
±
0.18
10
±
0.20
12
±
0.24
14
±
0.28
15
±
0.30
20
±
0.40
25
±
0.50
30
±
0.60
35
±
0.70
40
±
0.80
GATE
(GB)
t
EO
CLOCK 1
(C1)
t
GR
t
DO
1/f
0
CLOCK 2
(C2)
t
CS
Figure 1: Timing Diagram
©
1998 Data Delay Devices
NOTE: Any dash number
between 2 and 40 not shown
is also available.
Doc #98002
3/17/98
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
DLO32F
APPLICATION NOTES
THERMAL STABILITY
The delay line used internally to develop the clock
signals in the DLO32F has a thermal coefficient
of 100ppm/C. For low frequency units, this is also
the thermal coefficient of the output frequency.
For higher frequency units, however, other
internal effects must be considered, and the
actual thermal coefficient may be somewhat
higher.
POWER SUPPLY BYPASSING
The DLO32F relies on a stable power supply to
produce a repeatable frequency within the stated
tolerances. A 0.1uf capacitor from VCC to GND,
located as close as possible to the VCC pin, is
recommended. A wide VCC trace and a clean
ground plane should be used.
DEVICE SPECIFICATIONS
TABLE 1: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Storage Temperature
Lead Temperature
SYMBOL
V
CC
V
IN
T
STRG
T
LEAD
MIN
-0.3
-0.3
-55
MAX
7.0
V
DD
+0.3
150
300
UNITS
V
V
C
C
NOTES
10 sec
TABLE 2: DC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER
High Level Output Voltage
Low Level Output Voltage
High Level Output Current
Low Level Output Current
High Level Input Voltage
Low Level Input Voltage
Input Clamp Voltage
Input Current at Maximum
Input Voltage
High Level Input Current
Low Level Input Current
Short-circuit Output Current
Output High Fan-out
Output Low Fan-out
SYMBOL
V
OH
V
OL
I
OH
I
OL
V
IH
V
IL
V
IK
I
IHH
I
IH
I
IL
I
OS
MIN
2.5
TYP
3.4
0.35
MAX
UNITS
V
V
mA
mA
V
V
V
mA
µA
mA
mA
Unit
Load
NOTES
V
CC
= MIN, I
OH
= MAX
V
IH
= MIN, V
IL
= MAX
V
CC
= MIN, I
OL
= MAX
V
IH
= MIN, V
IL
= MAX
0.5
-1.0
20.0
2.0
0.8
-1.2
0.1
20
-0.6
-150
25
12.5
V
CC
= MIN, I
I
= I
IK
V
CC
= MAX, V
I
= 7.0V
V
CC
= MAX, V
I
= 2.7V
V
CC
= MAX, V
I
= 0.5V
V
CC
= MAX
-60
TABLE 3: AC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER
Enable to Clock On (Inherent Delay)
Disable to Clock Off
Clock Skew
Gate Recovery Time
SYMBOL
t
EO
t
DO
t
CS
t
GR
MIN
1.5
1.5
1.5
50
TYP
3.0
2.5
2.5
MAX
4.5
3.5
3.5
UNITS
ns
ns
ns
% of Clock Period
Doc #98002
3/17/98
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
2
DLO32F
PACKAGE DIMENSIONS
14
10
8
Lead Material:
Nickel-Iron alloy 42
TIN PLATE
14
10
8
.410
TYP.
1
7
1
7
.780 MAX.
.280
MAX.
.290
MAX.
.820 MAX.
.020 .320
TYP. MAX.
.130
±.030
.018 TYP.
.600 TYP.
.200
TYP.
.015 TYP.
.010±.002
.018
TYP.
.070 MAX.
.600±.010
.350
MAX.
.020 TYP.
.300
TYP.
DLO32F-xx (Commercial DIP)
DLO32F-xxM (Military DIP)
.020 TYP.
.040
TYP.
10
.010 TYP.
14
.020 TYP.
10
8
.040
TYP.
.270
TYP.
.050 TYP.
.320
TYP.
.270
TYP.
7
.430
TYP.
1
7
.090
.600
.790 MAX.
.300
MAX.
.050
TYP.
.110
.200
.600
.790 MAX.
.350
MAX.
.110
TYP.
DLO32F-xxA2 (Commercial Gull-Wing)
DLO32F-xxB2 (Commercial J-Lead)
.650
.100
1
14
.017
.510
MAX.
.100
1
14
.017
.510
MAX.
.300
TYP.
7
8
.300
TYP.
7
8
.100
.300
.200 MAX. (Com)
.225 MAX. (Mil)
.065
TYP.
.360
TYP.
.065
TYP.
.510 MAX.
.300
.050
.100
.080
.510 MAX.
.050
.080
.025
.008
.200 MAX. (Com)
.225 MAX. (Mil)
.005
.008
.045
.360 TYP.
.065 TYP.
.065 TYP.
DLO32F-xxD1 (Commercial SMD)
DLO32F-xxMD1 (Military SMD)
DLO32F-xxD4 (Commercial SMD)
DLO32F-xxMD4 (Military SMD)
Doc #98002
3/17/98
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
DLO32F
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
o
o
Ambient Temperature:
25 C
±
3 C
Supply Voltage (Vcc):
5.0V
±
0.1V
Input Pulse:
High = 3.0V
±
0.1V
Low = 0.0V
±
0.1V
Source Impedance:
50Ω Max.
Rise/Fall Time:
3.0 ns Max. (measured
between 0.6V and 2.4V )
Pulse Width Low:
PW
IN
= 10 x Clock Period
Period:
PER
IN
= 20 x Clock Period
OUTPUT:
Load:
C
load
:
Threshold:
1 FAST-TTL Gate
5pf
±
10%
1.5V (Rising & Falling)
NOTE:
The above conditions are for test only and do not in any way restrict the operation of the device.
FREQUENCY
COUNTER
PULSE
GENERATOR
OUT
TRIG
GB
DEVICE UNDER
TEST (DUT)
C1
C2
IN
TRIG
OSCILLOSCOPE
Test Setup
PER
IN
PW
IN
T
FALL
INPUT
SIGNAL
2.4V
1.5V
0.6V
2.4V
1.5V
0.6V
T
RISE
V
IH
V
IL
T
EO
OUTPUT
SIGNAL
V
OH
1.5V
1.5V
V
OL
Timing Diagram For Testing
Doc #98002
3/17/98
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
4
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