Enhanced
Features
s
s
s
Memory Systems Inc.
DM1M36SJ/DM1M32SJ
1Mbx36/1Mbx32 Enhanced DRAM
SIMM
Product Specification
Architecture
The DM1M36SJ achieves
1Mb x 36 density by mounting
nine 1Mb x 4 EDRAMs,
packaged in 28-pin plastic
SOJ packages, on a multi-
layer substrate. Eight DM2202
devices and one DM2212
device provide data and parity
storage. The DM1M32SJ
contains eight DM2202
devices for data only.
The EDRAM memory
module architecture is very
similar to a standard 4MB
DRAM module with the
Description
addition of an integrated
The Enhanced Memory Systems 4MB EDRAM SIMM module
cache and on-chip control which allows it to operate much like a
provides a single memory module solution for the main memory or
page mode or static column DRAM.
local memory of fast PCs, workstations, servers, and other high
The EDRAM’s SRAM cache is integrated into the DRAM array as
performance systems. Due to its fast 12ns cache row register, the
tightly coupled row registers. Memory reads always occur from the
EDRAM memory module supports zero-wait-state burst read
operations at up to 50MHz bus rates in a non-interleave configuration cache row register. When the on-chip comparator detects a page hit,
only the SRAM is accessed and data is available in 12ns from column
and 100MHz bus rates with a two-way interleave configuration.
address. When a page read miss is detected, the entire new DRAM
On-chip write posting and fast page mode operation supports
row is loaded into the cache and data is available at the output all
12ns write and burst write operations. On a cache miss, the fast
DRAM array reloads the entire 2KByte cache over a 2KByte-wide bus within 30ns from row enable. Subsequent reads within the page
(burst reads or random reads) will continue at 12ns cycle time.
in 18ns for an effective bandwidth of 113.6 Gbytes/sec. This means
very low latency and fewer wait states on a cache miss than a non-
Since reads occur from the SRAM cache, the DRAM precharge can
integrated cache/DRAM solution. The JEDEC compatible 72-bit SIMM occur simultaneously without degrading performance. The on-chip
configuration allows a single memory controller to be designed to
refresh counter with independent refresh bus allows the EDRAM to be
support either JEDEC slow DRAMs or high speed EDRAMs to provide refreshed during cache reads.
a simple upgrade path to higher system performance.
Memory writes are internally posted in 12ns and directed to the
DRAM array. During a write hit, the on-
chip address comparator activates a
Functional Diagram
parallel write path to the SRAM cache to
A
0-8
Column
maintain coherency. The EDRAM delivers
/CAL
0-3,P
Add
Column Decoder
12ns cycle page mode memory writes.
Latch
512 X 36 Cache (Row Register)
Memory writes do not affect the contents
11-Bit
Comp
of the cache row register except during a
Sense Amps
cache hit.
/G
& Column Write Select
I/O
By integrating the SRAM cache as
Last
Control
A
0-10
Row
DQ
0-35
and
row registers in the DRAM array and
Read
Data
Add
keeping the on-chip control simple, the
Latches
Latch
/S
EDRAM is able to provide superior
Memory
Row
performance over standard slow 4Mb
Array
/WE
Add
2048 x 512 x 36
Latch
DRAMs. By eliminating the need for
SRAMs and cache controllers, system
cost, board space, and power can all be
V
reduced.
2KByte SRAM Cache Memory for 12ns Random Reads Within a Page
Fast DRAM Array for 30ns Access to Any New Page
Write Posting Register for 12ns Random Writes and Burst Writes
Within a Page (Hit or Miss)
s
2KByte Wide DRAM to SRAM Bus for 113.6 Gigabytes/Sec Cache Fill
s
On-chip Cache Hit/Miss Comparators Maintain Cache Coherency
on Writes
s
Hidden Precharge and Refresh Cycles
s
Extended 64ms Refresh Period for Low Standby Power
s
Standard CMOS/TTL Compatible I/O Levels and +5 or 3.3V Volt Supply
s
Compatibility with JEDEC 1M x 36 DRAM SIMM Configuration
Allows Performance Upgrade in System
s
Low Power, Self Refresh Option
s
Industrial Temperature Range Option
Row Decoder
/F
W/R
/RE
0,2
Row Add
and
Refresh
Control
A
0-9
CC
C
1-9
Refresh
Counter
V
SS
The information contained herein is subject to change without notice.
Enhanced reserves the right to change or discontinue this product without notice.
© 1996 Enhanced Memory Systems Inc.
1850 Ramtron Drive, Colorado Springs, CO
Telephone
(800) 545-DRAM,
Fax
(719) 488-9095; http://www.csn.net/ramtron/enhanced
80921
38-2103-001
address to the LRR address latch (an 11-bit latch loaded on each
/RE active read cycle). If the row address does not match the LRR,
The EDRAM is designed to provide optimum memory
the requested data is not in SRAM cache and a new row must be
performance with high speed microprocessors. As a result, it is
fetched from the DRAM. The EDRAM will load the new row data
possible to perform simultaneous operations to the DRAM and
into the SRAM cache and update the LRR latch. The data at the
SRAM cache sections of the EDRAM. This feature allows the
specified column address is available at the output pins at the
EDRAM to hide precharge and refresh operation during SRAM
greater of times t
RAC
, t
AC
, and t
GQV
. It is possible to bring /RE high
cache reads and maximize SRAM cache hit rate by maintaining
after time t
RE
since the new row data is safely latched into SRAM
valid cache contents during write operations even if data is written cache. This allows the EDRAM to precharge the DRAM array while
to another memory page. These new functions, in conjunction
data is accessed from SRAM cache. It is possible to access
with the faster basic DRAM and cache speeds of the EDRAM,
additional SRAM cache locations by providing new column
minimize processor wait states.
addresses to the multiplex address inputs. New data is available at
the output at time t
AC
after each column address change in static
column mode. During read cycles, it is possible to operate in
EDRAM Basic Operating Modes
either static column mode with /CAL=high or page mode with
The EDRAM operating modes are specified in the table
/CAL clocked to latch the column address. In page mode, data
below.
valid is determined by either t
AC
or t
CQV
.
Hit and Miss Terminology
DRAM Write Hit
In this datasheet, “hit” and “miss” always refer to a hit or
If a DRAM write request is initiated by clocking /RE while
miss to the page of data contained in the SRAM cache row
W/R and /F are high, the EDRAM will compare the new row
register. This is always equal to the contents of the last row that
address to the LRR address latch (an 11-bit address latch loaded
was read from (as modified by any write hit data). Writing to a
on each /RE active read). If the row address matches, the EDRAM
new page does not cause the cache to be modified.
will write data to both the DRAM array and selected SRAM cache
simultaneously to maintain coherency. The write address and data
DRAM Read Hit
If a DRAM read request is initiated by clocking /RE with W/R are posted to the DRAM as soon as the column address is latched
by bringing /CAL low and the write data is latched by bringing /WE
low and /F and /CAL high, the EDRAM will compare the new row
low (both /CAL and /WE must be high when initiating the write
address to the last row read address latch (LRR; an 11-bit latch
loaded on each /RE active read cycle). If the row address matches cycle with the falling edge of /RE). The write address and data can
the LRR, the requested data is already in the SRAM cache and no be latched very quickly after the fall of /RE (t
RAH
+ t
ASC
for the
column address and t
DS
for the data). During a write burst
DRAM memory reference is initiated. The data specified by the
sequence, the second write data can be posted at time t
RSW
after
column address is available at the output pins at the greater of
/RE. Subsequent writes within a page can occur with write cycle
times t
AC
or t
GQV
. Since no DRAM activity is initiated, /RE can be
brought high after time t
RE1
, and a shorter precharge time, t
RP1
, is time t
PC
. With /G enabled and /WE disabled, it is possible to
required. It is possible to access additional SRAM cache locations perform cache read operations while the /RE is activated in write
hit mode. This allows read-modify-write, write-verify, or random
by providing new column addresses to the multiplex address
read-write sequences within the page with 12ns cycle times (the
inputs. New data is available at the output at time t
AC
after each
first read cannot complete until after time t
RAC2
). At the end of a
column address change in static column mode. During read
write sequence (after /CAL and /WE are brought high and t
RE
is
cycles, it is possible to operate in either static column mode with
satisfied), /RE can be brought high to precharge the memory. It is
/CAL=high or page mode with /CAL clocked to latch the column
possible to perform cache reads concurrently with precharge.
address. In page mode, data valid time is determined by either t
AC
During write sequences, a write operation is not performed unless
or t
CQV
.
both /CAL and /WE are low. As a result, the /CAL input can be used
as a byte write select in multi-chip systems. If /CAL is not clocked
DRAM Read Miss
If a DRAM read request is initiated by clocking /RE with W/R on a write sequence, the memory will perform a /RE only refresh
to the selected row and data will remain unmodified.
low and /F and /CAL high, the EDRAM will compare the new row
EDRAM Basic Operating Modes
Function
Read Hit
Read Miss
Write Hit
Write Miss
Internal Refresh
Low Power Standby
Unallowed Mode
Low Power Self-Refresh
Option
Functional Description
/S
L
L
L
L
X
H
H
H
/RE
↓
↓
↓
↓
↓
H
L
↓
W/R
L
L
H
H
X
X
X
H
/F
H
H
H
H
L
X
H
H
/CAL
H
H
H
H
X
H
X
L
/WE
X
X
H
H
X
H
X
H
A
0-10
Row = LRR
Row
≠
LRR
Row = LRR
Row
≠
LRR
X
X
X
X
Comment
No DRAM Reference, Data in Cache
DRAM Row to Cache
Write to DRAM and Cache, Reads Enabled
Write to DRAM, Cache Not Updated, Reads Disabled
Cache Reads Enabled
Standby Current
Unallowed Mode (Except -L Option)
Standby Current, Internal Refresh Clock (-L Option)
H = High; L = Low; X = Don’t Care;
↓
= High-to-Low Transition; LRR = Last Row Read
1-62
DRAM Write Miss
If a DRAM write request is initiated by clocking /RE while W/R
and /F are high, the EDRAM will compare the new row address to
the LRR address latch (an 11-bit latch loaded on each /RE active
read cycle). If the row address does not match, the EDRAM will
write data to the DRAM array only and contents of the current
cache is not modified. The write address and data are posted to the
DRAM as soon as the column address is latched by bringing /CAL
low and the write data is latched by bringing /WE low (both /CAL
and /WE must be high when initiating the write cycle with the
falling edge of /RE). The write address and data can be latched very
quickly after the fall of /RE (t
RAH
+ t
ASC
for the column address and
t
DS
for the data). During a write burst sequence, the second write
data can be posted at time t
RSW
after /RE. Subsequent writes within
a page can occur with write cycle time t
PC
. During a write miss
sequence, cache reads are inhibited and the output buffers are
disabled (independently of /G) until time t
WRR
after /RE goes high.
At the end of a write sequence (after /CAL and /WE are brought
high and t
RE
is satisfied), /RE can be brought high to precharge the
memory. It is possible to perform cache reads concurrently with
the precharge. During write sequences, a write operation is not
performed unless both /CAL and /WE are low. As a result, /CAL can
be used as a byte write select in multi-chip systems. If /CAL is not
clocked on a write sequence, the memory will perform a /RE only
refresh to the selected row and data will remain unmodified.
/RE Inactive Operation
It is possible to read data from the SRAM cache without
clocking /RE. This option is desirable when the external control
logic is capable of fast hit/miss comparison. In this case, the
controller can avoid the time required to perform row/column
multiplexing on hit cycles. This capability also allows the EDRAM to
perform cache read operations during precharge and refresh
cycles to minimize wait states. It is only necessary to select /S and
/G and provide the appropriate column address to read data as
shown in the table below. The row address of the SRAM cache
accessed without clocking /RE will be specified by the LRR address
latch loaded during the last /RE active read cycle. To perform a
cache read in static column mode, /CAL is held high, and the cache
contents at the specified column address will be valid at time t
AC
after address is stable. To perform a cache read in page mode,
/CAL is clocked to latch the column address. The cache data is
valid at time t
AC
after the column address is setup to /CAL.
Internal Refresh
If /F is active (low) on the assertion of /RE, an internal refresh
cycle is executed. This cycle refreshes the row address supplied by
an internal refresh counter. This counter is incremented at the end
of the cycle in preparation for the next /F refresh cycle. At least
1,024 /F cycles must be executed every 64ms. /F refresh cycles can
be hidden because cache memory can be read under column
address control throughout the entire /F cycle. /F cycles are the
only active cycles during which /S can be disabled.
/CAL Before /RE Refresh (“/CAS Before /RAS”)
/CAL before /RE refresh, a special case of internal refresh, is
discussed in the “Reduced Pin Count Operation” section below.
/RE Only Refresh Operation
Although /F refresh using the internal refresh counter
is the recommended method of EDRAM refresh, it is
possible to perform an /RE only refresh using an externally
supplied row address. /RE refresh is performed by executing
a
write cycle
(W/R and /F are high) where /CAL is not clocked.
This is necessary so that the current cache contents and LRR are
not modified by the refresh operation. All combinations of
addresses A
0-9
must be sequenced every 64ms refresh period. A
10
does not need to be cycled. Read refresh cycles are not allowed
because a DRAM refresh cycle does not occur when a read refresh
address matches the LRR address latch.
+3.3 Volt Power Supply Operation
If the +3.3 volt power supply option is specified, the EDRAM
will operate from a +3.3 volt ±0.3 volt power supply and all inputs
and outputs will have LVTTL/LVCMOS compatible signal levels. The
+3.3 volt EDRAM will not accept input levels which exceed the
power supply voltage. If mixed I/O levels are expected in your
system, please specify the +5 volt version of the EDRAM.
Low Power Mode
The EDRAM enters its low power mode when /S is high. In this
mode, the internal DRAM circuitry is powered down to reduce
standby current.
Low Power, Self-Refresh Option
When the low power, self refresh mode option is specified
when ordering the EDRAM, the EDRAM enters this mode when /RE
is clocked while /S, W/R, /F, and /WE are high; and /CAL is low. In
this mode, the power is turned off to all I/O pins except /RE to
Function
/S
/G
/CAL
A
0-8
minimize chip power, and an on-board refresh clock is enabled to
Cache Read (Static Column)
L
L
H
Column Address
perform self-refresh cycles using the on-board refresh counter. The
Cache Read (Page Mode)
L
L
¤
Column Address
EDRAM remains in this low power mode until /RE is brought high
again to terminate the mode. The EDRAM /RE input must remain
H = High; L = Low; X = Don’t Care;
¤
= Transitioning
high for t
RP2
following exit from self-refresh mode to allow any on-
Write-Per-Bit Operation
going internal refresh to terminate prior to the next memory
The DM1M36SJ EDRAM SIMM provides a write-per-bit
operation.
capability to selectively modify individual parity bits (DQ
8,17,26,35
)
Initialization Cycles
for byte write operations. The parity device (DM2212) is selected
A minimum of 10 initialization (start-up) cycles are required
via /CAL
P
. Data bits do not require or support write-per-bit
before normal operation is guaranteed. A combination of eight /F
capability. Byte write selection to non-parity bits is accomplished
via /CAL
0-3
. The bits to be written are determined by a bit mask data
refresh cycles and two read cycles to different row addresses are
word which is placed on the parity I/O data pins prior to clocking
necessary to complete initialization. /RE must be high for 300ns
prior to initialization.
/RE. The logic one bits in the mask data select the bits to be
written. As soon as the mask is latched by /RE, the mask data is
Unallowed Mode
removed and write data can be placed on the databus. The mask is
Read, write, or /RE only refresh operations must not be initiated
only specified on the /RE transition. During page mode burst write
to unselected memory banks by clocking /RE when /S is high.
operations, the same mask is used for all write operations.
1-63
Interconnect Diagram
DQ 13
DQ 18
DQ 22
DQ 31
DQ 4
10
11
12
14
15
16
17
19
20
21
23
24
25
26
27
28
29
30
32
33
34
/CAL
DQ0
DQ1
DQ2
DQ3
U6
U3
Byte 2
DM2202J
1Mb x 4
DM2202J
1Mb x 4
DM2202J
1Mb x 4
48
47
68
69
67
/CAL
/RE
16
/CAL
/RE
16
16
40
43
41
42
46
44
34
/CAL0
/CAL1
/CAL2
/CAL3
/CALP
/RE0
/RE2
/CAL0
/CAL1
/CAL2
/CAL3
/CALP
+5V (+3.3V)
10
11
30
59
66
1
29
39
71
72
70
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
PD
C1
C2
C3
6
C4
C5
6
C6
6
W/R
/WE
/F
/S0
/G
17
20
18
19
23
W/R
/WE
/F
/S
/G
DM2202J
1Mb x 4
DM2202J
1Mb x 4
/CAL
/RE
12
13
14
15
16
17
18
28
31
32
19
16
/CAL
/RE
EDRAM
16
EDRAM
C7
C8
6
C9
*DM2212 is not present on the DM1M32SJ.
1-64
6
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
1
2
12
3
4
5
9
10
11
13
15
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
DM2202J
1Mb x 4
/CAL
/RE
16
/CAL
/RE
16
U1
Byte 1
EDRAM
/CAL
/RE
16
/CAL
/RE
16
EDRAM
6
6
EDRAM
6
EDRAM
6
EDRAM
/RE
2
4
6
8
20
22
24
26
36
49
51
53
55
57
61
63
65
37
3
5
7
9
21
23
25
27
35
50
52
54
56
58
60
62
64
38
27
26
25
24
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ 35
DQ 0
Edge
Connecter
J1
5
6
1
2
3
7
8
9
27
26
25
DQ0
DQ1
DQ2
27
26
25
DQ0
DQ1
DQ2
27
26
25
24
DQ3
24
DQ0
DQ1
DQ2
27
26
25
24
DQ3
U8
U7
Parity
U5
*
DM2212J
1Mb x 4
DQ0
DQ1
DQ2
27
26
25
24
DQ3
DQ3
24
+5V (+3.3V)
VCC 7
VCC 14
VCC 22
8
VSS 21
VSS 28
VSS
DQ0
DQ1
DQ2
27
26
25
24
DQ3
DQ0
DQ1
DQ2
27
26
25
24
DQ3
U4
U2
Byte 4
DM2202J
1Mb x 4
DM2202J
1Mb x 4
DQ0
DQ1
DQ2
DQ3
27
26
25
24
EDRAM
DQ0
DQ1
DQ2
DQ3
U9
Byte 3
EDRAM
Pinout
Interconnect
Pin No. Function (Component Pin)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
GND
DQ
0
DQ
18
DQ
1
DQ
19
DQ
2
DQ
20
DQ
3
DQ
21
+5/3.3 V
+5/3.3 V
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
10
DQ
4
DQ
22
DQ
5
DQ
23
DQ
6
DQ
24
DQ
7
DQ
25
A
7
GND
+5/3.3 V
A
8
A
9
NC
/RE
2
DQ
26
*
DQ
8
*
U2,4,5,7,8 (6)
U5 (27)
U5 (26)
C (8, 21, 28)
U1 (27)
U2 (24)
U1 (26)
U2 (25)
U1 (25)
U2 (26)
U1 (24)
U2 (27)
C (7, 14, 22)
C (7, 14, 22)
C (1)
C (2)
C (12)
C (3)
C (4)
C (5)
C (9)
C (15)
U3 (27)
U4 (24)
U3 (26)
U4 (25)
U3 (25)
U4 (26)
U3 (24)
U4 (27)
C (10)
C (8, 21, 28)
C (7, 14, 22)
C (11)
C (13)
Organization
Ground
Byte 1 I/O 1
Byte 3 I/O 1
Byte 1 I/O 2
Byte 3 I/O 2
Byte 1 I/O 3
Byte 3 I/O 3
Byte 1 I/O 4
Byte 3 I/O 4
V
CC
V
CC
Address
Address
Address
Address
Address
Address
Address
Address
Byte 1 I/O 5
Byte 3 I/O 5
Byte 1 I/O 6
Byte 3 I/O 6
Byte 1 I/O 7
Byte 3 I/O 7
Byte 1 I/O 8
Byte 3 I/O 8
Address
Ground
V
CC
Address
Address
Reserved for 2Mb x 36
Row Enable (Bytes 3,4, Parity)
Parity I/O for Byte 3
Parity I/O for Byte 1
Interconnect
Pin No. Function (Component Pin)
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
DQ
17
*
DQ
35
*
GND
/CAL
0
/CAL
2
/CAL
3
/CAL
1
/RE
0
NC
/CAL
P
*
/WE
W/R
DQ
9
DQ
27
DQ
10
DQ
28
DQ
11
DQ
29
DQ
12
DQ
30
DQ
13
DQ
31
+5/3.3 V
DQ
32
DQ
14
DQ
33
DQ
15
DQ
34
DQ
16
+5/3.3 V
/G
/F
/S
PD
GND
GND
U5 (16)
C (20)
C (17)
U6 (27)
U7 (27)
U6 (26)
U7 (26)
U6 (25)
U7 (25)
U6 (24)
U7 (24)
U9 (24)
U8 (27)
C (7, 14, 22)
U8 (26)
U9 (25)
U8 (25)
U9 (26)
U8 (24)
U9 (27)
C (7, 14, 22)
C (23)
C (18)
C (19)
Signal GND
C (8, 21, 28)
C (8, 21, 28)
U5 (25)
U5 (24)
C (8, 21, 28)
U1,3 (16)
U2,4 (16)
U7,8 (16)
U6,9 (16)
U1,3,6,9 (6)
Organization
Parity I/O for Byte 2
Parity I/O for Byte 4
Ground
Byte 1 Column Address Latch
Byte 3 Column Address Latch
Byte 4 Column Address Latch
Byte 2 Column Address Latch
Row Enable (Bytes 1,2)
Reserved for 2Mb x 36
Parity Column Address Latch
Write Enable
W/R Mode Control
Byte 2 I/O 1
Byte 4 I/O 1
Byte 2 I/O 2
Byte 4 I/O 2
Byte 2 I/O 3
Byte 4 I/O 3
Byte 2 I/O 4
Byte 4 I/O 4
Byte 2 I/O 5
Byte 4 I/O 5
V
CC
Byte 4 I/O 6
Byte 2 I/O 6
Byte 4 I/O 7
Byte 2 I/O 7
Byte 4 I/O 8
Byte 2 I/O 8
V
CC
Output Enable
Refresh Mode Control
Chip Select
Presence Detect
Ground
Ground
*No Connect for DM1M32SJ
C = Common to All Memory Chips, U1 = Chip 1, etc.
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