Enhanced
Features
s
Memory Systems Inc.
DM4M32SJ
4Mb x 32 Enhanced DRAM SIMM
Product Specification
Architecture
The DM4M32SJ achieves
4Mb x 32 density by mounting
32 4M x 1 EDRAMs, packaged
in 28-pin plastic SOJ packages
on both sides of the multi-
layer substrate. Four buffers
have been added to reduce the
loading on the address and
control lines. The buffers have
balanced output current levels
and current limiting resistors.
These offer low ground
Description
bounce, minimal undershoot,
and controlled fall times.
The Enhanced Memory Systems 16MB EDRAM SIMM module
The EDRAM memory
provides a single memory module solution for the main memory or
module architecture is very
local memory of fast PCs, workstations, servers, and other high
similar to a standard 16MB DRAM module with the addition of an
performance systems. Due to its fast 12ns cache row register, the
integrated cache and on-chip control which allows it to operate much
EDRAM memory module supports zero-wait-state burst read
operations at up to 66MHz bus rates in a non-interleave configuration like a page mode or static column DRAM.
The EDRAM's SRAM cache is integrated into the DRAM array as
and >100MHz bus rates with a two-way interleave configuration.
tightly coupled row registers. Memory reads always occur from the
On-chip write posting and fast page mode operation supports
cache row register. When the on-chip comparator detects a page hit,
12ns write and burst write operations. On a cache miss, the fast
DRAM array reloads the entire 8Kbyte cache over an 8Kbyte-wide bus only the SRAM is accessed and data is available in 12ns from column
in 18ns for an effective bandwidth of 454 Gbytes/sec. This means very address. When a page read miss is detected, the entire new DRAM row
is updated into the cache and data is available at the output all within
low latency and fewer wait states on a cache miss than a non-
a single 30ns access. Subsequent reads within the page (burst reads,
integrated cache/DRAM solution. The JEDEC compatible SIMM
local instructions, or data) will continue at 12ns cycle time. Since reads
configuration allows a single memory controller to be designed to
support either JEDEC slow DRAMs or high speed EDRAMs to provide occur from the SRAM cache, DRAM precharge can occur simultaneously
without degrading performance. The on-chip refresh counter with
a simple upgrade path to higher system performance.
independent refresh bus allows the EDRAM to
be refreshed during cache reads.
DM4M32SJ Functional Diagram
Memory writes are internally posted in
12ns and directed to the DRAM array. During
A
0-10
Column
CAL
0-3
Add
Column Decoder
a write hit, the on-chip address comparator
Latch
activates a parallel write path to the SRAM
2048 X 32 Cache (Row Register)
11-Bit
cache to maintain coherency. The EDRAM
Comp
Sense Amps
delivers 12ns cycle page mode memory writes.
G
& Column Write Select
I/O
Last
Memory writes do not affect the contents of
Control
Row
DQ
0-31
and
Read
A
0-10
the cache row register except during a cache
Data
Add
Latches
Latch
hit.
S
By integrating the SRAM cache as row
Memory
Row
Array
WE
Add
registers in the DRAM array and keeping the
16Mbyte
Latch
on-chip control simple, the EDRAM is able to
provide superior performance over standard
V
slow DRAMs.
A
0-9
C
Integrated 2,048 x 32 SRAM Cache Row Register Allows 12ns
Access Random Reads Within the Page
s
Interleaved SRAM Cache for 8ns Burst Reads
s
30ns DRAM Array for Fast Random Access to Any Page
s
Ultra-Fast Integrated 8Kbyte-Wide DRAM to Cache Bus
for 454-Gbyte/sec Cache Fill Bandwidth
s
On-Chip Write Posting and Fast Page Mode Operation Allows
12ns Writes and Burst Writes
s
On-Board Address and Control Buffering
s
Low Power Self Refresh Mode Option
Row Decoder
CC
F
W/R
RE
0,2
Row Add
and
Refresh
Control
1-36
Refresh
Counter
V
SS
PD
PD16M
The information contained herein is subject to change without notice. Enhanced reserves the right
to change or discontinue this product without notice.
© 1996 Enhanced Memory Systems Inc.,
1850 Ramtron Drive, Colorado Springs, CO 80921
Telephone
(800) 545-DRAM;
Fax
(719) 488-9095; http://www.csn.net/ramtron/enhanced
38-2110-002
DRAM Read Miss
If a DRAM read request is initiated by clocking /RE with W/R
The EDRAM is designed to provide optimum memory
low and /F and /CAL high, the EDRAM will compare the new row
performance with high speed microprocessors. As a result, it is
address to the LRR address latch (an 11-bit latch loaded on each
possible to perform simultaneous operations to the DRAM and
SRAM cache sections of the EDRAM. This feature allows the EDRAM /RE active read cycle). If the row address does not match the LRR,
to hide precharge and refresh operation during SRAM cache reads the requested data is not in SRAM cache and a new row must be
fetched from the DRAM. The EDRAM will load the new row data
and maximize SRAM cache hit rate by maintaining valid cache
contents during write operations even if data is written to another
into the SRAM cache and update the LRR latch. The data at the
memory page. These new functions, in conjunction with the faster specified column address is available at the output pins at the
basic DRAM and cache speeds of the EDRAM, minimize processor greater of times t
RAC
, t
AC
, and t
GQV
. It is possible to bring /RE high
wait states.
after time t
RE
since the new row data is safely latched into SRAM
cache. This allows the EDRAM to precharge the DRAM array while
EDRAM Basic Operating Modes
data is accessed from SRAM cache. It is possible to access
The EDRAM operating modes are specified in the table below. additional SRAM cache locations by providing new column
addresses to the multiplex address inputs. New data is available at
Hit and Miss Terminology
the output at time t
AC
after each column address change in static
In this datasheet, “hit” and “miss” always refer to a hit or miss column mode. During read cycles, it is possible to operate in either
to the page of data contained in the SRAM cache row register. This static column mode with /CAL=high or page mode with /CAL
is always equal to the contents of the last row that was read from
clocked to latch the column address. In page mode, data valid
(as modified by any write hit data). Writing to a new page does not time is determined by either t
AC
or t
CQV
.
cause the cache to be modified.
DRAM Write Hit
DRAM Read Hit
If a DRAM write request is initiated by clocking /RE while W/R
If a DRAM read request is initiated by clocking /RE with W/R
and /F are high, the EDRAM will compare the new row address to
low and /F and /CAL high, the EDRAM will compare the new row
the LRR address latch (an 11-bit address latch loaded on each /RE
address to the last row read address latch (LRR; an 11-bit latch
active read). If the row address matches, the EDRAM will write data
loaded on each /RE active read cycle). If the row address matches to both the DRAM array and selected SRAM cache simultaneously
the LRR, the requested data is already in the SRAM cache and no
to maintain coherency. The write address and data are posted to
DRAM memory reference is initiated. The data specified by the
the DRAM as soon as the column address is latched by bringing
column address is available at the output pins at the greater of
/CAL low and the write data is latched by bringing /WE low (both
times t
AC
or t
GQV
. Since no DRAM activity is initiated, /RE can be
/CAL and /WE must be high when initiating the write cycle with the
brought high after time t
RE1
, and a shorter precharge time, t
RP1
, is falling edge of /RE). The write address and data can be latched very
required. It is possible to access additional SRAM cache locations
quickly after the fall of /RE (t
RAH
+ t
ASC
for the column address and
by providing new column addresses to the multiplex address
t
DS
for the data). During a write burst sequence, the second write
inputs. New data is available at the output at time t
AC
after each
data can be posted at time t
RSW
after /RE. Subsequent writes within
column address change in static column mode. During read cycles, a page can occur with write cycle time t . With /G enabled and
PC
it is possible to operate in either static column mode with
/WE disabled, it is possible to perform cache read operations while
/CAL=high or page mode with /CAL clocked to latch the column
the /RE is activated in write hit mode. This allows read-modify-
address. In page mode, data valid time is determined by either t
AC
write, write-verify, or random read-write sequences within the page
or t
CQV
.
with 12ns cycle times (the first read cannot complete until after
time t
RAC2
). At the end of a write sequence (after /CAL and /WE are
brought high and t
RE
is satisfied), /RE can be brought high to
Functional Description
EDRAM Basic Operating Modes
Function
Read Hit
Read Miss
Write Hit
Write Miss
Internal Refresh
Low Power Standby
Unallowed Mode
Low Power Self
Refresh Option
/S
L
L
L
L
X
H
H
H
/RE
↓
↓
↓
↓
↓
H
L
↓
W/R
L
L
H
H
X
X
X
X
/F
H
H
H
H
L
X
H
H
/CAL
H
H
H
H
X
H
X
L
/WE
X
X
H
H
X
H
X
H
A
0-10
Row = LRR
Row
≠
LRR
Row = LRR
Row
≠
LRR
X
X
X
X
Comment
No DRAM Reference, Data in Cache
DRAM Row to Cache
Write to DRAM and Cache, Reads Enabled
Write to DRAM, Cache Not Updated, Reads Disabled
Cache Reads Enabled
Standby Current
Unallowed Mode (Except -L Option)
Standby Current, Internal Refresh Clock
H = High; L = Low; X = Don’t Care;
↓
= High-to-Low Transition; LRR = Last Row Read
1-106
On-Chip SRAM Interleave
The DM4M32 has an on-chip interleave of its SRAM cache
which allows 8ns random accesses (t
AC1
) for up to three data
words (burst reads) following an initial read access (hit or miss).
The SRAM cache is integrated into the DRAM arrays in a 512 x 128
organization. It is converted into a 2K x 32 page organization by
using an on-chip address multiplexer to select one of four 32-bit
words to the output pins DQ
0-31
(as shown below). The specific
DRAM Write Miss
If a DRAM write request is initiated by clocking /RE while W/R word selected to the output is determined by column addresses A
o
and A
1
. System operation is consistent with the standard
and /F are high, the EDRAM will compare the new row address to
“Functional Description” and timing diagrams shown in this
the LRR address latch (an 11-bit latch loaded on each /RE active
specification. See the note in the read timing diagrams and
read cycle). If the row address does not match, the EDRAM will
“Switching Characteristics” chart for the faster access and data
write data to the DRAM array only and contents of the current
cache is not modified. The write address and data are posted to the hold times.
DM4M32 Datapath Architecture
DRAM as soon as the column address is latched by bringing /CAL
low and the write data is latched by bringing /WE low (both /CAL
and /WE must be high when initiating the write cycle with the
32
Row Address
falling edge of /RE). The write address and data can be latched very
4M DRAM Arrays
A
0-10
quickly after the fall of /RE (t
RAH
+ t
ASC
for the column address and
65,538 Bits
t
DS
for the data). During a write burst sequence, the second write
data can be posted at time t
RSW
after /RE. Subsequent writes within
32
a page can occur with write cycle time t
PC
. During a write miss
Column Address
2K SRAM Caches
A
2-10
sequence, cache reads are inhibited and the output buffers are
disabled (independently of /G) until time t
WRR
after /RE goes high.
128 Bits
At the end of a write sequence (after /CAL and /WE are brought
high and t
RE
is satisfied), /RE can be brought high to precharge the
Column Address
4 to 1
memory. It is possible to perform cache reads concurrently with
A
0,
A
1
Output Selector
the precharge. During write sequences, a write operation is not
32 Bits
performed unless both /CAL and /WE are low. As a result, /CAL can
be used as a byte write select in multi-chip systems. If /CAL is not
clocked on a write sequence, the memory will perform a /RE only
Q
refresh to the selected row and data will remain unmodified.
/RE Inactive Operation
Internal Refresh
It is possible to read data from the SRAM cache without
If /F is active (low) on the assertion of /RE, an internal refresh
clocking /RE. This option is desirable when the external control
cycle is executed. This cycle refreshes the row address supplied by
logic is capable of fast hit/miss comparison. In this case, the
an internal refresh counter. This counter is incremented at the end
controller can avoid the time required to perform row/column
of the cycle in preparation for the next /F refresh cycle. At least
multiplexing on hit cycles. This capability also allows the EDRAM to 1,024 /F cycles must be executed every 64ms. /F refresh cycles can
perform cache read operations during precharge and refresh
be hidden because cache memory can be read under column
cycles to minimize wait states. It is only necessary to select /S and
address control throughout the entire /F cycle. /F cycles are the
/G and provide the appropriate column address to read data as
only active cycles during which /S can be disabled.
shown in the table below. The row address of the SRAM cache
accessed without clocking /RE will be specified by the LRR address
/CAL Before /RE Refresh (“/CAS Before /RAS”)
latch loaded during the last /RE active read cycle. To perform a
/CAL before /RE refresh, a special case of internal refresh, is
cache read in static column mode, /CAL is held high, and the cache discussed in the “Reduced Pin Count Operation” section below.
contents at the specified column address will be valid at time t
AC
/RE Only Refresh Operation
after address is stable. To perform a cache read in page mode,
/CAL is clocked to latch the column address. The cache data is
Although /F refresh using the internal refresh counter is the
valid at time t
AC
after the column address is setup to /CAL.
recommended method of EDRAM refresh, it is possible to perform
an /RE only refresh using an externally supplied row address. /RE
refresh is performed by executing a
write cycle
(W/R and /F are
Function
/S
/G
/CAL
A
0-10
high) where /CAL is not clocked. This is necessary so that the current
cache contents and LRR are not modified by the refresh operation.
Cache Read (Static Column)
L
L
H
Column Address
All combinations of addresses A
0
, A
2
- A
10
must be sequenced every
Cache Read (Page Mode)
L
L
¤
Column Address
64ms refresh period. A
1
does not need to be cycled. Read refresh
cycles are not allowed because a DRAM refresh cycle does not occur
H = High; L = Low; X = Don’t Care;
¤
= Transitioning
when a read refresh address matches the LRR address latch.
precharge the memory. It is possible to perform cache reads
concurrently with precharge. During write sequences, a write
operation is not performed unless both /CAL and /WE are low. As a
result, the /CAL input can be used as a byte write select in multi-
chip systems. If /CAL is not clocked on a write sequence, the
memory will perform a /RE only refresh to the selected row and
data will remain unmodified.
1-107
Low Power Self Refresh
When the low power, self-refresh option is specified when
ordering the EDRAM, the EDRAM enters this mode when /RE is
clocked while /S, W/R, /F, and /WE are high; and /CAL is low. In
this mode, the power is turned off to all I/O pins except /RE to
minimize chip power and an on-board refresh clock is enabled to
perform self-refresh cycles using the on-board refresh counter.
The EDRAM remains in this low power mode until /RE is brought
high again to terminate the mode. The EDRAM /RE input must
remain high for t
RP2
following exit from self-refresh mode to allow
any on-going internal refresh to terminate prior to the next
memory operation.
Low Power Mode
The EDRAM enters its low power mode when /S is high. In this
mode, the internal DRAM circuitry is powered down to reduce
standby current to 34mA.
Initialization Cycles
A minimum of 10 initialization (start-up) cycles are required
before normal operation is guaranteed. A combination of eight /F
refresh cycles and two read cycles to different row addresses are
necessary to complete initialization. /RE must be high for 300ns
prior to initialization.
Unallowed Mode
Read, write, or /RE only refresh operations must not be
initiated to unselected memory banks by clocking /RE when /S is
high.
Reduced Pin Count Operation
It is possible to simplify the interface to the 16 MByte SIMM to
reduce the number of control lines. /REO and /RE2 could be tied
together externally to provide a single row enable. W/R and /G can
be tied together if reads are not performed during write hit cycles.
This external wiring simplifies the interface without any
performance impact.
/F — Refresh
This input will initiate a DRAM refresh operation using the
internal refresh counter as an address source when it is low on the
low going edge of /RE.
/WE — Write Enable
This input controls the latching of write data on the input data
pins. A write operation is initiated when both /CAL and /WE are low.
/G — Output Enable
This input controls the gating of read data to the output data
pins during read operations.
/S — Chip Select
This input is used to power up the I/O and clock circuitry.
When /S is high, the EDRAM remains in its low power mode. /S
must remain active throughout any read or write operation. With
the exception of /F refresh cycles, /RE
0,2
should never be clocked
when /S is inactive.
DQ
0 -31
— Data Input/Output
These bidirectional pins are used to read and write data to the
EDRAM.
PD — Presence Detect
This signal is grounded to indicate the presence of SIMM
module in the socket.
PD16M — 16M Presence Detect
This signal is grounded to indicate the presence of a 16M
SIMM. A 4 or 8 MB SIMM has this pin open.
A
0-10
— Multiplex Address
These inputs are used to specify the row and column
addresses of the EDRAM data. The 11-bit row address is latched on
the falling edge of /RE. The 11-bit column address can be specified
at any other time to select read data from the SRAM cache or to
specify the write column address during write cycles. A
0,1
are used
to select one of four interleaved data words during read
operations.
Pin Descriptions
/RE
0, 2
— Row Enable
V
CC
Power Supply
These inputs are used to initiate DRAM read and write
These inputs are connected to the +5 volt power supply.
operations and latch a row address as well as the states of W/R and
/F. It is not necessary to clock /RE
0, 1
to read data from the EDRAM
V
SS
Ground
SRAM row registers. On read operations, /RE
0, 1
can be brought
These inputs are connected to the power supply ground
high as soon as data is loaded into cache to allow early precharge. connection.
/REO controls Bytes 1 and 2. /RE2 controls Bytes 3 and 4.
/CAL
0 -3
— Column Address Latch
These inputs are used to latch the column address and in
combination with /WE to trigger write operations. When /CAL is
high, the column address latch is transparent. When /CAL is low,
the column address is closed and the output of the latch contains
the address present while /CAL was high. /CAL can be toggled when
/RE is low or high. However, /CAL must be high during the high-to-
low transition of /RE except for /F refresh cycles. /CAL
0-3
controls
Bytes 1-4 respectively.
W/R — Write/Read
This input along with /F specifies the type of DRAM operation
initiated on the low going edge of /RE. When /F is high, W/R
specifies either a write (logic high) or read operation (logic low).
1-108
Pinout
Pin No. Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
GND
DQ
0
DQ
18
DQ
1
DQ
19
DQ
2
DQ
20
DQ
3
DQ
21
+5 Volts
+5 Volts
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
10
DQ
4
DQ
22
DQ
5
DQ
23
DQ
6
DQ
24
DQ
7
DQ
25
A
7
GND
+5 Volts
A
8
A
9
NC
RE
2
GND
GND
Organization
Ground
Byte 1 I/O 1
Byte 3 I/O 1
Byte 1 I/O 2
Byte 3 I/O 2
Byte 1 I/O 3
Byte 3 I/O 3
Byte 1 I/O 4
Byte 3 I/O 4
V
CC
V
CC
Address
Address
Address
Address
Address
Address
Address
Address
Byte 1 I/O 5
Byte 3 I/O 5
Byte 1 I/O 6
Byte 3 I/O 6
Byte 1 I/O 7
Byte 3 I/O 7
Byte 1 I/O 8
Byte 3 I/O 8
Address
Ground
V
CC
Address
Address
Not Connected
Row Enable (Bytes 3, 4)
Ground
Ground
Pin No. Function
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
+5 Volts
GND
GND
CAL
0
CAL
2
CAL
3
CAL
1
RE
0
NC
PD16M
WE
W/R
DQ
9
DQ
27
DQ
10
DQ
28
DQ
11
DQ
29
DQ
12
DQ
30
DQ
13
DQ
31
+5 Volts
DQ
32
DQ
14
DQ
33
DQ
15
DQ
34
DQ
16
+5 Volts
G
F
S
PD
GND
GND
Signal GND
Signal GND
V
CC
Organization
Ground
Ground
Byte 1 Column Address Latch
Byte 3 Column Address Latch
Byte 4 Column Address Latch
Byte 2 Column Address Latch
Row Enable (Bytes 1, 2)
Not Connected
Ground
Write Enable
W/R Mode Control
Byte 2 I/O 1
Byte 4 I/O 1
Byte 2 I/O 2
Byte 4 I/O 2
Byte 2 I/O 3
Byte 4 I/O 3
Byte 2 I/O 4
Byte 4 I/O 4
Byte 2 I/O 5
Byte 4 I/O 5
V
CC
Byte 4 I/O 6
Byte 2 I/O 6
Byte 4 I/O 7
Byte 2 I/O 7
Byte 4 I/O 8
Byte 2 I/O 8
V
CC
Output Enable
Refresh Mode Control
Chip Select
Presence Detect
Ground
Ground
1-109
