DM74ALS165 8-Bit Parallel In/Serial Out Shift Register
January 1986
Revised February 2000
DM74ALS165
8-Bit Parallel In/Serial Out Shift Register
General Description
The DM74ALS165 is an 8-bit serial register that, when
clocked, shifts the data toward serial output, Q
H
. Parallel-in
access to each stage is provided by eight individual direct
data inputs that are enabled by a low level at the SH/LD
input. The DM74ALS165 also features a clock inhibit func-
tion and a complemented serial output, Q
H
.
Clocking is accomplished by a LOW-to-HIGH transition of
the CLK input while SH/LD is held HIGH and CLK INH is
held LOW. The functions of the CLK and CLK INH (clock
inhibit) inputs are interchangeable. Since a LOW CLK input
and a LOW-to-HIGH transition of CLK INH will also accom-
plish clocking, CLK INH should be changed to the high
level only while the CLK input is HIGH. Parallel loading is
inhibited when SH/LD is held HIGH. The parallel inputs to
the register are enabled while SH/LD is LOW indepen-
dently of the levels of CLK, CLK INH, or SER inputs.
Features
s
Complementary outputs
s
Direct overriding load (data) inputs
s
Gated clock inputs
s
Parallel-to-serial data conversion
Ordering Code:
Order Number
DM74ALS165M
DM74ALS165N
Package Number
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Inputs
Shift/ Clock Clock Serial Parallel
Load Inhibit
L
H
H
H
H
H
H
X
L
L
L
↑
↑
H
X
L
↑
↑
L
L
X
X
X
H
L
H
L
X
A...H
a...h
X
X
X
X
X
X
Internal
Outputs
Q
A
a
Q
A0
H
L
H
L
Q
A0
Q
B
b
Q
B0
Q
An
Q
An
Q
An
Q
An
Q
B0
Output
Q
H
h
Q
H0
Q
Gn
Q
Gn
Q
Gn
Q
Gn
Q
H0
H
=
HIGH Level (steady-state),
L
=
LOW Level (steady-state)
X
=
Don't Care (any input, including transitions)
↑ =
Transition from LOW-to-HIGH level
a...h
=
The level of steady-state input at inputs A through H, respectively
Q
A0
, Q
B0
, Q
H0
=
The level of Q
A
, Q
B
, or Q
H
, respectively, before the
indicated steady-state input conditions were established
Q
An
, Q
Gn
=
The level of Q
A
or Q
G
, respectively, before the most recent
↑
transition of the clock
© 2000 Fairchild Semiconductor Corporation
DS006712
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DM74ALS165
Logic Diagram
Timing Diagram
Typical Shift, Load, and Inhibit Sequences
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2
DM74ALS165
Absolute Maximum Ratings
(Note 1)
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
Storage Temperature Range
Typical
θ
JA
N Package
M Package
74.0°C/W
104.0°C/W
7V
7V
0°C to
+70°C
−65°C
to
+150°C
Note 1:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Symbol
V
CC
V
IH
V
IL
I
OH
I
OL
f
CLOCK
t
W
Supply Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Current
LOW Level Output Current
Clock Frequency
Pulse Duration
CLK HIGH
CLK LOW
Load
t
SU
t
SU
t
H
T
A
Setup Time
Setup Time
Hold Time
Operating Free Air Temperature
SH/LD
Data
CLK INH
↓
before CLK
Serial before CLK
45
11
11
12
10
10
11
10
4
0
70
ns
ns
ns
°C
ns
Parameter
Min
4.5
2
0.8
−0.4
8
Typ
5
Max
5.5
Units
V
V
V
mA
mA
MHz
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
V
IK
V
OH
V
OL
I
I
I
IH
I
IL
I
O
(Note 3)
I
CC
Parameter
Input Clamp Voltage
HIGH Level
Output Voltage
LOW Level
Output Voltage
Input Current at Max Input Voltage V
CC
=
5.5V, V
I
=
7V
HIGH Level Input Current
LOW Level Input Current
Output Drive Current
Supply Current
V
CC
=
5.5V, V
I
=
2.7V
V
CC
=
5.5V, V
I
=
0.4V
V
CC
=
5.5V, V
O
=
2.25V
V
CC
=
5.5V (Note 4)
−30
16
Conditions
V
CC
=
4.5V, I
I
= −18
mA
I
OH
= −0.4
mA
V
CC
=
4.5V to 5.5V
V
CC
=
4.5V
I
OL
=
4 mA
I
OL
=
8 mA
V
CC
−
2
0.25
0.35
0.4
0.5
0.1
20
−0.1
−112
24
Min
Typ
(Note 2)
Max
−1.5
Units
V
V
V
mA
µA
mA
mA
mA
Note 2:
All typical values are at V
CC
=
5V, T
A
=
25°C.
Note 3:
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
OS
.
Note 4:
With the outputs open, CLK INH and CLK at 4.5V, and a clock pulse applied to the SH/LD input, I
CC
is measured first with the parallel inputs at 4.5V,
then with the parallel inputs grounded.
3
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DM74ALS165
Switching Characteristics
over recommended free air temperature range. All typical values are measured at V
CC
=
5V, T
A
=
25°C.
Symbol
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
Parameter
Maximum Frequency
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Load
Q
H
or Q
H
Q
H
or Q
H
Q
H
or Q
H
Q
H
or Q
H
Q
H
Q
H
Q
H
Q
H
Input
Output
Conditions
V
CC
=
4.5V to 5.5V,
C
L
=
50 pF,
R
L
=
500Ω
T
A
=
Min to Max
Min
45
4
Typ
60
13
20
ns
4
14
22
Max
Units
MHz
Load
CLK
3
7
13
ns
CLK
H
H
3
3
3
9
7
9
14
13
ns
16
H
2
8
15
ns
H
3
9
16
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4
DM74ALS165
Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
5
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