DM74LS221 Dual Non-Retriggerable One-Shot with Clear and Complementary Outputs
February 1992
DM74LS221 Dual Non-Retriggerable One-Shot
with Clear and Complementary Outputs
General Description
The DM74LS221 is a dual monostable multivibrator with
Schmitt-trigger input Each device has three inputs permit-
ting the choice of either leading-edge or trailing-edge trig-
gering Pin (A) is an active-low trigger transition input and
pin (B) is an active-high transition Schmitt-trigger input that
allows jitter free triggering for inputs with transition rates as
slow as 1 volt second This provides the input with excellent
noise immunity Additionally an internal latching circuit at the
input stage also provides a high immunity to V
CC
noise The
clear (CLR) input can terminate the output pulse at a prede-
termined time independent of the timing components This
(CLR) input also serves as a trigger input when it is pulsed
with a low level pulse transition (
) To obtain the best
and trouble free operation from this device please read op-
erating rules as well as the NSC one-shot application notes
carefully and observe recommendations
Y
Y
Y
Y
Y
Y
Y
Pin-out identical to ’LS123 (Note 1)
Output pulse width range from 30 ns to 70 seconds
Hysteresis provided at (B) input for added noise
immunity
Direct reset terminates output pulse
Triggerable from CLEAR input
DTL TTL compatible
Input clamp diodes
Note 1
The pin-out is identical to ’LS123 but functionally it is not refer to
Operating Rules 10 in this datasheet
Functional Description
The basic output pulse width is determined by selection of
an external resistor (R
X
) and capacitor (C
X
) Once triggered
the basic pulse width is independent of further input tran-
sitions and is a function of the timing components or it may
be reduced or terminated by use of the active low CLEAR
input Stable output pulse width ranging from 30 ns to 70
seconds is readily obtainable
Features
Y
Y
A dual highly stable one-shot
Compensated for V
CC
and temperature variations
Connection Diagram
Dual-In-Line Package
Function Table
Inputs
CLEAR
L
X
X
H
H
A
X
H
X
L
B
X
X
L
Q
L
L
L
Outputs
Q
H
H
H
u
H
H
v
L
u
H
e
High Logic Level
L
e
Low Logic Level
X
e
Can Be Either Low or High
u
e
Positive Going Transition
v
e
Negative Going Transition
e
A Positive Pulse
e
A Negative Pulse
TL F 6409 – 1
This mode of triggering requires first the B input be set from a low to high
level while the CLEAR input is maintained at logic low level Then with the B
input at logic high level the CLEAR input whose positive transition from low
to high will trigger an output pulse
Order Number DM74LS221M or DM74LS221N
See NS Package Number M16A or N16A
TL F 6409 – 2
C
1995 National Semiconductor Corporation
TL F 6409
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
(Note)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
7V
Input Voltage
Operating Free Air Temperature Range
DM74LS
Storage Temperature Range
7V
0 C to
a
70 C
b
65 C to
a
150 C
Note
The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed The device should not be operated at these limits The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation
Recommended Operating Conditions
Symbol
V
CC
V
T
a
V
T
b
V
T
a
V
T
b
I
OH
I
OL
t
W
t
REL
dV
dt
dV
dt
R
EXT
C
EXT
DC
Supply Voltage
Positive-Going Input Threshold Voltage
at the A Input (V
CC
e
Min)
Negative-Going Input Threshold Voltage
at the A Input (V
CC
e
Min)
Positive-Going Input Threshold Voltage
at the B Input (V
CC
e
Min)
Negative-Going Input Threshold Voltage
at the B Input (V
CC
e
Min)
High Level Output Current
Low Level Output Current
Pulse Width
(Note 1)
Clear Release Time (Note 1)
Rate of Rise or Fall of
Schmitt Input (B) (Note 1)
Rate of Rise or Fall of
Logic Input (A) (Note 1)
External Timing Resistor (Note 1)
External Timing Capacitance (Note 1)
Duty Cycle
(Note 1)
Free Air Operating Temperature
R
T
e
2 kX
R
T
e
R
EXT
(Max)
0
14
0
Data
Clear
40
40
15
1
1
100
1000
50
60
70
C
ns
V
s
V
ms
kX
mF
%
08
08
Parameter
Min
4 75
DM74LS221
Nom
5
1
1
1
09
b
0 4
Units
Max
5 25
2
V
V
V
2
V
V
mA
mA
ns
8
T
A
Note 1
T
A
e
25 C and V
CC
e
5V
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
V
I
V
OH
V
OL
Parameter
Input Clamp Voltage
High Level Output
Voltage
Low Level Output
Voltage
Conditions
V
CC
e
Min I
I
e b
18 mA
V
CC
e
Min
V
IL
e
Max
I
OH
e
Max
V
IH
e
Min
27
34
0 35
05
04
01
mA
Min
Typ
(Note 1)
Max
b
1 5
Units
V
V
V
CC
e
Min I
OL
e
Max
V
IL
e
Max V
IH
e
Min
V
CC
e
Min I
OL
e
4 mA
V
CC
e
Max V
I
e
7V
V
I
I
Input Current
Input Voltage
Max
2
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) (Continued)
Symbol
I
IH
I
IL
Parameter
High Level Input Current
Low Level Input
Current
Conditions
V
CC
e
Max V
I
e
2 7V
V
CC
e
Max
V
I
e
0 4V
A1 A2
B
Clear
I
OS
I
CC
Short Circuit
Output Current
Supply Current
V
CC
e
Max
(Note 2)
V
CC
e
Max
Quiescent
Triggered
Note 1
All typicals are at V
CC
e
5V T
A
e
25 C
Note 2
Not more than one output should be shorted at a time and the duration should not exceed one second
Min
Typ
(Note 1)
Max
20
b
0 4
b
0 8
b
0 8
Units
mA
mA
b
20
b
100
mA
mA
47
19
11
27
Switching Characteristics
at V
CC
e
5V and T
A
e
25 C
Symbol
t
PLH
t
PLH
t
PHL
t
PHL
t
PLH
t
PHL
t
W(out)
Parameter
Propagation Delay Time
Low to High Level Output
Propagation Delay Time
Low to High Level Output
Propagation Delay Time
High to Low Level Output
Propagation Delay Time
High to Low Level Output
Propagation Delay Time
Low to High Level Output
Propagation Delay Time
High to Low Level Output
Output Pulse
Width Using Zero
Timing Capacitance
Output Pulse
Width Using External
Timing Resistor
From (Input)
To (Output)
A1 A2
to Q
B
to Q
A1 A2
to Q
B
to Q
Clear to
Q
Clear
to Q
A1 A2
to Q Q
C
EXT
e
0
R
EXT
e
2 kX
R
L
e
2 kX
C
L
e
15 pF
C
EXT
e
100 pF
R
EXT
e
10 kX
R
L
e
2 kX
C
L
e
15 pF
C
EXT
e
1
mF
R
EXT
e
10 kX
R
L
e
2 kX
C
L
e
15 pF
C
EXT
e
80 pF
R
EXT
e
2 kX
R
L
e
2 kX
C
L
e
15 pF
Conditions
C
EXT
e
80 pF
R
EXT
e
2 kX
C
L
e
15 pF
R
L
e
2 kX
Min
Max
70
55
80
65
65
55
Units
ns
ns
ns
ns
ns
ns
20
70
ns
t
W(out)
A1 A2
to Q Q
600
750
ns
6
75
ms
70
150
ns
3
Operating Rules
1 An external resistor (R
X
) and an external capacitor (C
X
)
are required for proper operation The value of C
X
may
vary from 0 to approximately 1000
mF
For small time
constants high-grade mica glass polypropylene polycar-
bonate or polystyrene material capacitor may be used
For large time constants use tantalum or special alumi-
num capacitors If timing capacitor has leakages ap-
proaching 100 nA or if stray capacitance from either ter-
minal to ground is greater than 50 pF the timing equations
may not represent the pulse width the device generates
2 When an electrolytic capacitor is used for C
X
a switching
diode is often required for standard TTL one-shots to pre-
vent high inverse leakage current This switching diode is
not needed for the ’LS221 one-shot and should not be
used
Furthermore if a polarized timing capacitor is used on the
’LS221 the positive side of the capacitor should be con-
nected to the ‘‘C
EXT
’’ pin
(Figure 1 )
5 For C
X
k
1000 pF see
Figure 3
for T
W
vs C
X
family
curves with R
X
as a parameter
TL F 6409 – 4
FIGURE 3
6 To obtain variable pulse widths by remote trimming the
following circuit is recommended
TL F 6409 – 5
Note
‘‘R
remote
’’ should be as close to the one-shot as possible
FIGURE 4
TL F 6409 – 8
FIGURE 1
3 For C
X
ll
1000 pF the output pulse width (T
W
) is de-
fined as follows
T
W
e
KR
X
C
X
where R
X
is in kX
C
X
is in pF
T
W
is in ns
K
Ln2
e
0 70
4 The multiplicative factor K is plotted as a function of C
X
below for design considerations
7 Output pulse width versus V
CC
and temperatures
Figure
5
depicts the relationship between pulse width variation
versus V
CC
Figure 6
depicts pulse width variation versus
temperatures
TL F 6409 – 6
FIGURE 5
TL F 6409 – 3
FIGURE 2
TL F 6409 – 7
FIGURE 6
4
Operating Rules
(Continued)
8 Duty cycle is defined as T
W
T
c
100 in percentage if it
goes above 50% the output pulse width will become
shorter If the duty cycle varies between low and high
values this causes output pulse width to vary or jitter (a
function of the R
EXT
only) To reduce jitter R
EXT
should
be as large as possible for example with R
EXT
e
100k
jitter is not appreciable until the duty cycle approaches
90%
9 Under any operating condition C
X
and R
X
must be kept
as close to the one-shot device pins as possible to mini-
mize stray capacitance to reduce noise pick-up and to
reduce I-R and Ldi dt voltage developed along their con-
necting paths If the lead length from C
X
to pins (6) and
(7) or pins (14) and (15) is greater than 3 cm for exam-
ple the output pulse width might be quite different from
values predicted from the appropriate equations A non-
inductive and low capacitive path is necessary to ensure
complete discharge of C
X
in each cycle of its operation
so that the output pulse width will be accurate
10 Although the ’LS221’s pin-out is identical to the ’LS123
it should be remembered that they are not functionally
identical The ’LS123 is a retriggerable device such that
the output is dependent upon the input transitions when
its output ‘‘Q’’ is at the ‘‘High’’ state Furthermore it is
recommended for the ’LS123 to externally ground the
C
EXT
pin for improved system performance However
this pin on the ’LS221 is not an internal connection to
the device ground Hence if substitution of an ’LS221
onto an ’LS123 design layout where the C
EXT
pin is
wired to the ground the device will not function
11 V
CC
and ground wiring should conform to good high-
frequency standards and practices so that switching
transients on the V
CC
and ground return leads do not
cause interaction between one-shots A 0 01
mF
to 0 10
mF
bypass capacitor (disk ceramic or monolithic type)
from V
CC
to ground is necessary on each device Fur-
thermore the bypass capacitor should be located as
close to the V
CC
-pin as space permits
For further detailed device characteristics and output performance
please refer to the NSC one-shot application note AN-372
Physical Dimensions
inches (millimeters)
16-Lead Small Outline Molded Package (M)
Order Number DM74LS221M
NS Package Number M16A
5
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