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DP83848Q PHYTER Extended Temperature Single Port 10/100 Mb/s Ethernet Physical Layer
Transceiver
September 19, 2011
DP83848Q
PHYTER Extended Temperature Single Port 10/100 Mb/s
Ethernet Physical Layer Transceiver
1.0 General Description
The number of applications requiring Ethernet connectivity
continues to increase, driving Ethernet enabled devices into
harsher environments.
The DP83848Q was designed to meet the challenge of these
new applications with an extended temperature performance
that goes beyond the typical Industrial temperature range.
The DP83848Q is a highly reliable, feature rich, robust device
which meets IEEE 802.3u standards over an EXTENDED
temperature range of -40°C to 105°C. This device is ideally
suited for harsh environments such as automotive/transporta-
tion, wireless remote base stations,and industrial control ap-
plications.
It offers enhanced ESD protection and the choice of an MII or
RMII interface for maximum flexibility in MPU selection; all in
a 40 pin LLP package.
The DP83848Q extends the leadership position of the
PHYTER family of devices with a wide operating temperature
range. The National Semiconductor line of PHYTER
transceivers builds on decades of Ethernet expertise to offer
the high performance and flexibility that allows the end user
an easy implementation tailored to meet these application
needs.
3.0 Features
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AEC-Q100 Grade 2
Extreme Temperature from -40°C to 105°C
Low-power 3.3V, 0.18µm CMOS technology
Low power consumption <270mW Typical
3.3V MAC Interface
Auto-MDIX for 10/100 Mb/s
Energy Detection Mode
25 MHz clock out
RMII Rev. 1.2 Interface (configurable)
MII Serial Management Interface (MDC and MDIO)
IEEE 802.3u MII
IEEE 802.3u Auto-Negotiation and Parallel Detection
IEEE 802.3u ENDEC, 10BASE-T transceivers and filters
IEEE 802.3u PCS, 100BASE-TX transceivers and filters
IEEE 1149.1 JTAG
Integrated ANSI X3.263 compliant TP-PMD physical sub-
layer with adaptive equalization and Baseline Wander
compensation
Error-free Operation up to 150 meters
Programmable LED support for Link and Activity
Single register access for complete PHY status
10/100 Mb/s packet BIST (Built in Self Test)
Lead free 40-pin LLP package (6mm) x (6mm) ADC
2.0 Applications
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Automotive/Transportation
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Industrial Controls and Factory Automation
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General Embedded Applications
4.0 System Diagram
30152551
PHYTER
®
is a registered trademark of National Semiconductor.
© 2011 National Semiconductor Corporation
301525
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DP83848Q
4.0 Block Diagram
30152501
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DP83848Q
Table of Contents
1.0 General Description ......................................................................................................................... 1
2.0 Applications .................................................................................................................................... 1
3.0 Features ........................................................................................................................................ 1
4.0 System Diagram .............................................................................................................................. 1
4.0 Block Diagram ................................................................................................................................ 2
6.0 Pin Layout ...................................................................................................................................... 6
7.0 Pin Descriptions .............................................................................................................................. 7
7.1 SERIAL MANAGEMENT INTERFACE ........................................................................................ 7
7.2 MAC DATA INTERFACE ........................................................................................................... 7
7.3 CLOCK INTERFACE ................................................................................................................ 8
7.4 LED INTERFACE ..................................................................................................................... 9
7.5 RESET ................................................................................................................................... 9
7.6 STRAP OPTIONS .................................................................................................................. 10
7.7 10 Mb/s AND 100 Mb/s PMD INTERFACE ................................................................................ 11
7.8 SPECIAL CONNECTIONS ...................................................................................................... 11
7.9 POWER SUPPLY PINS .......................................................................................................... 11
7.10 PACKAGE PIN ASSIGNMENTS ............................................................................................. 12
8.0 Configuration ................................................................................................................................ 13
8.1 AUTO-NEGOTIATION ............................................................................................................ 13
8.1.1 Auto-Negotiation Pin Control .......................................................................................... 13
8.1.2 Auto-Negotiation Register Control ................................................................................... 13
8.1.3 Auto-Negotiation Parallel Detection ................................................................................. 13
8.1.4 Auto-Negotiation Restart ............................................................................................... 14
8.1.5 Enabling Auto-Negotiation via Software ........................................................................... 14
8.1.6 Auto-Negotiation Complete Time .................................................................................... 14
8.2 AUTO-MDIX .......................................................................................................................... 14
8.3 PHY ADDRESS ..................................................................................................................... 14
8.3.1 MII Isolate Mode ........................................................................................................... 14
8.4 LED INTERFACE ................................................................................................................... 15
8.4.1 LEDs .......................................................................................................................... 15
8.4.2 LED Direct Control ........................................................................................................ 16
8.5 HALF DUPLEX vs. FULL DUPLEX ........................................................................................... 16
8.6 INTERNAL LOOPBACK .......................................................................................................... 16
8.7 BIST ..................................................................................................................................... 16
9.0 Functional Description .................................................................................................................... 17
9.1 MII INTERFACE ..................................................................................................................... 17
9.1.1 Nibble-wide MII Data Interface ....................................................................................... 17
9.1.2 Collision Detect ............................................................................................................ 17
9.1.3 Carrier Sense .............................................................................................................. 17
9.2 REDUCED MII INTERFACE .................................................................................................... 17
9.3 802.3u MII SERIAL MANAGEMENT INTERFACE ...................................................................... 18
9.3.1 Serial Management Register Access ............................................................................... 18
9.3.2 Serial Management Access Protocol ............................................................................... 18
9.3.3 Serial Management Preamble Suppression ...................................................................... 19
10.0 Architecture ................................................................................................................................ 20
10.1 100BASE-TX TRANSMITTER ................................................................................................ 20
10.1.1 Code-group Encoding and Injection ............................................................................... 21
10.1.2 Scrambler .................................................................................................................. 21
10.1.3 NRZ to NRZI Encoder ................................................................................................. 22
10.1.4 Binary to MLT-3 Convertor ........................................................................................... 22
10.2 100BASE-TX RECEIVER ...................................................................................................... 22
10.2.1 Analog Front End ........................................................................................................ 22
10.2.2 Digital Signal Processor ............................................................................................... 22
10.2.2.1 Digital Adaptive Equalization and Gain Control ..................................................... 23
10.2.2.2 Base Line Wander Compensation ....................................................................... 24
10.2.3 Signal Detect ............................................................................................................. 25
10.2.4 MLT-3 to NRZI Decoder .............................................................................................. 25
10.2.5 NRZI to NRZ .............................................................................................................. 25
10.2.6 Serial to Parallel ......................................................................................................... 25
10.2.7 Descrambler .............................................................................................................. 25
10.2.8 Code-group Alignment ................................................................................................ 25
10.2.9 4B/5B Decoder ........................................................................................................... 25
10.2.10 100BASE-TX Link Integrity Monitor ............................................................................. 25
10.2.11 Bad SSD Detection ................................................................................................... 25
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DP83848Q
10.3 10BASE-T TRANSCEIVER MODULE .....................................................................................
10.3.1 Operational Modes .....................................................................................................
10.3.2 Smart Squelch ...........................................................................................................
10.3.3 Collision Detection and SQE ........................................................................................
10.3.4 Carrier Sense .............................................................................................................
10.3.5 Normal Link Pulse Detection/Generation ........................................................................
10.3.6 Jabber Function .........................................................................................................
10.3.7 Automatic Link Polarity Detection and Correction ............................................................
10.3.8 Transmit and Receive Filtering .....................................................................................
10.3.9 Transmitter ................................................................................................................
10.3.10 Receiver ..................................................................................................................
11.0 Design Guidelines .......................................................................................................................
11.1 TPI NETWORK CIRCUIT ......................................................................................................
11.2 ESD PROTECTION ..............................................................................................................
11.3 CLOCK IN (X1) REQUIREMENTS ..........................................................................................
11.4 POWER FEEDBACK CIRCUIT ..............................................................................................
11.5 ENERGY DETECT MODE .....................................................................................................
12.0 Reset Operation ..........................................................................................................................
12.1 HARDWARE RESET ............................................................................................................
12.2 SOFTWARE RESET .............................................................................................................
13.0 Register Block .............................................................................................................................
13.1 REGISTER DEFINITION .......................................................................................................
13.1.1 Basic Mode Control Register (BMCR) ............................................................................
13.1.2 Basic Mode Status Register (BMSR) .............................................................................
13.1.3 PHY Identifier Register #1 (PHYIDR1) ...........................................................................
13.1.4 PHY Identifier Register #2 (PHYIDR2) ...........................................................................
13.1.5 Auto-Negotiation Advertisement Register (ANAR) ...........................................................
13.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page) .............................
13.1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page) ...............................
13.1.8 Auto-Negotiate Expansion Register (ANER) ...................................................................
13.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR) ...............................................
13.2 EXTENDED REGISTERS ......................................................................................................
13.2.1 PHY Status Register (PHYSTS) ...................................................................................
13.2.2 False Carrier Sense Counter Register (FCSCR) .............................................................
13.2.3 Receiver Error Counter Register (RECR) .......................................................................
13.2.4 100 Mb/s PCS Configuration and Status Register (PCSR) ................................................
13.2.5 RMII and Bypass Register (RBR) ..................................................................................
13.2.6 LED Direct Control Register (LEDCR) ...........................................................................
13.2.7 PHY Control Register (PHYCR) ....................................................................................
13.2.8 10 Base-T Status/Control Register (10BTSCR) ...............................................................
13.2.9 CD Test and BIST Extensions Register (CDCTRL1) ........................................................
13.2.10 Energy Detect Control (EDCR) ...................................................................................
14.0 Absolute Maximum Ratings ...........................................................................................................
15.0 AC and DC Specifications .............................................................................................................
15.1 DC SPECIFICATIONS ..........................................................................................................
15.2 AC SPECIFICATIONS ..........................................................................................................
15.2.1 Power Up Timing ........................................................................................................
15.2.2 Reset Timing .............................................................................................................
15.2.3 MII Serial Management Timing .....................................................................................
15.2.4 100 Mb/s MII Transmit Timing ......................................................................................
15.2.5 100 Mb/s MII Receive Timing .......................................................................................
15.2.6 100BASE-TX and 100BASE-FX MII Transmit Packet Latency Timing ................................
15.2.7 100BASE-TX Transmit Packet Deassertion Timing ..........................................................
15.2.8 100BASE-TX Transmit Timing (t
R/F
& Jitter) ....................................................................
15.2.9 100BASE-TX Receive Packet Latency Timing ................................................................
15.2.10 100BASE-TX Receive Packet Deassertion Timing ........................................................
15.2.11 10 Mb/s MII Transmit Timing ......................................................................................
15.2.12 10 Mb/s MII Receive Timing .......................................................................................
15.2.13 10 Mb/s Serial Mode Transmit Timing ..........................................................................
15.2.14 10 Mb/s Serial Mode Receive Timing ..........................................................................
15.2.15 10BASE-T Transmit Timing (Start of Packet) ................................................................
15.2.16 10BASE-T Transmit Timing (End of Packet) .................................................................
15.2.17 10BASE-T Receive Timing (Start of Packet) .................................................................
15.2.18 10BASE-T Receive Timing (End of Packet) ..................................................................
15.2.19 10 Mb/s Heartbeat Timing .........................................................................................
15.2.20 10 Mb/s Jabber Timing .............................................................................................
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