DP8440V-40,DP8440V-40 pdf中文资料,DP8440V-40引脚图,DP8440V-40电路-Datasheet-电子工程世界

器件参数

参数名称

属性值

是否Rohs认证

不符合

包装说明

QCCJ, LDCC84,1.2SQ

Reach Compliance Code

unknow

地址总线宽度

边界扫描

最大时钟频率

40 MHz

外部数据总线宽度

JESD-30 代码

S-PQCC-J84

JESD-609代码

长度

29.3116 mm

低功率模式

内存组织

16M X 1

区块数量

端子数量

最高工作温度

70 °C

最低工作温度

封装主体材料

PLASTIC/EPOXY

封装代码

QCCJ

封装等效代码

LDCC84,1.2SQ

封装形状

SQUARE

封装形式

CHIP CARRIER

峰值回流温度（摄氏度）

NOT SPECIFIED

电源

5 V

认证状态

Not Qualified

座面最大高度

5.08 mm

最大压摆率

260 mA

最大供电电压

5.25 V

最小供电电压

4.75 V

标称供电电压

5 V

表面贴装

YES

技术

CMOS

温度等级

COMMERCIAL

端子面层

Tin/Lead (Sn/Pb)

端子形式

J BEND

端子节距

1.27 mm

端子位置

QUAD

处于峰值回流温度下的最长时间

NOT SPECIFIED

宽度

29.3116 mm

uPs/uCs/外围集成电路类型

MEMORY CONTROLLER, DRAM

Base Number Matches

文档预览

DP8440-40 DP8440-25 DP8441-40 DP8441-25 microCMOS Programmable 16 64 Mbit

Dynamic RAM Controller Driver

February 1995

DP8440-40 DP8440-25 DP8441-40 DP8441-25

microCMOS Programmable 16 64 Mbit

Dynamic RAM Controller Driver

General Description

The DP8440 41 Dynamic RAM Controllers provide an easy

interface between dynamic RAM arrays and 8- 16- 32- and

64-bit microprocessors The DP8440 41 DRAM Controllers

generate all necessary control and timing signals to suc-

cessfully interface and design dynamic memory systems

With significant enhancements over the DP8420 21 22

predecessors the DP8440 41 are suitable for high perform-

ance memory systems These controllers support page and

burst accesses for fast page static column and nibble

DRAMs Refreshes and accesses are arbitrated on chip

RAS low time during refresh and RAS precharge time are

guaranteed by these controllers Separate precharge coun-

ters for each RAS output avoid delayed back to back ac-

cesses due to precharge when using memory interleaving

Programmable features make the DP8440 41 DRAM Con-

trollers flexible enough to fit many memory systems

Features

40 MHz and 25 MHz operation

Page detection

Automatic CPU burst accesses

Support 1 4 16 64 Mbits DRAMs

High capacitance drivers for RAS CAS WE and Q out-

puts

Support for fast page static column and nibble mode

DRAMs

High precision PLL based delay line

Byte enable for word size up to 32 bits on the DP8440

or 64 bits on the DP8441

Automatic Internal Refresh

Staggered RAS-Only refresh

Burst and CAS-before-RAS refresh

Error scrubbing during refresh

TRI-STATE outputs

Easy interface to all major microprocessors

Block Diagram

TL F 11718 – 1

FIGURE 1

TRI-STATE is a registered trademark of National Semiconductor Corporation

1995 National Semiconductor Corporation

TL F 11718

RRD-B30M75 Printed in U S A

DRAM

Controller

DP8440V-40

DP8440VLJ-40

DP8440VLJ-25

DP8441VLJ-40

DP8441VLJ-25

Maximum Clock

Frequency

40 MHz

25 MHz

40 MHz

25 MHz

Package

Type

84-Pin PLCC

100-Pin PQFP

Bus Width

Supporting

8 16 32

8 16 32 64

Largest DRAM

Possible

16 Mbits

64 Mbits

Table of Contents

1 0 CONNECTION DIAGRAMS

2 0 FUNCTIONAL INTRODUCTION

3 0 SIGNAL DESCRIPTION

3 1 Address and Control Signals

3 2 DRAM Control Signals

3 3 Refresh Signals

3 4 Reset and Programming Signals

3 5 Clock Inputs

3 6 Power Signals and Capacitor Input

4 0 PROGRAMMING AND RESETTING

4 1 Reset

4 2 Programming Sequence

4 3 Programming Selection Bits

5 0 ACCESS MODES

5 1 Opening Access

5 2 Normal Mode

5 3 Page Mode

5 4 Burst Access

5 5 Inner Page Burst Access

6 0 REFRESH MODES

6 1 Auto-Internal Refresh

6 2 Externally Controlled Refresh

6 3 Error Scrubbing during Refresh

6 4 Extending Refresh

6 5 Refresh Types

7 0 WAIT SUPPORT

7 1 DTACK During Opening Access

7 2 DTACK During Page Access

7 3 DTACK During Burst Access

7 4 Next Address or Early DTACK Support

8 0 ABSOLUTE MAXIMUM RATINGS

9 0 DC ELECTRICAL CHARACTERISTICS

10 0 LOAD CAPACITANCE

11 0 AC TIMING PARAMETERS

12 0 AC TIMING WAVEFORMS

CLK and DECLK Timing

Refresh Timing

Refresh and Access Timing

Programming and Initialization Period Timing

Normal Mode Access Timing

Page Mode Access Timing

Burst Mode Access Timing

13 0 ERRATA

14 0 PHYSICAL DIMENSIONS

1 0 Connection Diagrams

TL F 11718 – 2

Top View

FIGURE 2

Order Number DP8441VLJ-40 (40 MHz Operation) DP8441VLJ-25 (25 MHz Operation)

See NS Package Number VLJ100A

1 0 Connection Diagrams

(Continued)

TL F 11718 – 38

Top View

FIGURE 3

Order Number DP8440VLJ-40 (40 MHz Operation) DP8440VLJ-25 (25 MHz Operation)

See NS Package Number VLJ100A

1 0 Connection Diagrams

(Continued)

TL F 11718 – 3

Top View

FIGURE 4

Order Number DP8440V-40 (40 MHz Operation)

See NS Package Number V84A

参数对比

与DP8440V-40相近的元器件有：DP8440-40、DP8440VLJ-25、DP8440VLJ-40、DP8441VLJ-25、DP8441VLJ-40。描述及对比如下：

型号	DP8440V-40	DP8440-40	DP8440VLJ-25	DP8440VLJ-40	DP8441VLJ-25	DP8441VLJ-40
描述	microCMOS Programmable 16/64 Mbit Dynamic RAM Controller/Driver	microCMOS Programmable 16/64 Mbit Dynamic RAM Controller/Driver	microCMOS Programmable 16/64 Mbit Dynamic RAM Controller/Driver	microCMOS Programmable 16/64 Mbit Dynamic RAM Controller/Driver	microCMOS Programmable 16/64 Mbit Dynamic RAM Controller/Driver	microCMOS Programmable 16/64 Mbit Dynamic RAM Controller/Driver
是否Rohs认证	不符合	-	不符合	不符合	不符合	不符合
包装说明	QCCJ, LDCC84,1.2SQ	-	QFP, QFP100,.7X.9	QFP, QFP100,.7X.9	QFP, QFP100,.7X.9	QFP, QFP100,.7X.9
Reach Compliance Code	unknow	-	unknow	unknow	unknow	unknow
地址总线宽度	24	-	24	24	26	26
边界扫描	NO	-	NO	NO	NO	NO
最大时钟频率	40 MHz	-	25 MHz	40 MHz	25 MHz	40 MHz
JESD-30 代码	S-PQCC-J84	-	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100
JESD-609代码	e0	-	e0	e0	e0	e0
长度	29.3116 mm	-	20 mm	20 mm	20 mm	20 mm
低功率模式	NO	-	NO	NO	NO	NO
内存组织	16M X 1	-	16M X 1	16M X 1	64M X 1	64M X 1
区块数量	4	-	4	4	4	4
端子数量	84	-	100	100	100	100
最高工作温度	70 °C	-	70 °C	70 °C	70 °C	70 °C
封装主体材料	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	QCCJ	-	QFP	QFP	QFP	QFP
封装等效代码	LDCC84,1.2SQ	-	QFP100,.7X.9	QFP100,.7X.9	QFP100,.7X.9	QFP100,.7X.9
封装形状	SQUARE	-	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	CHIP CARRIER	-	FLATPACK	FLATPACK	FLATPACK	FLATPACK
峰值回流温度（摄氏度）	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
电源	5 V	-	5 V	5 V	5 V	5 V
认证状态	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	5.08 mm	-	3 mm	3 mm	3 mm	3 mm
最大压摆率	260 mA	-	260 mA	260 mA	260 mA	260 mA
最大供电电压	5.25 V	-	5.25 V	5.25 V	5.25 V	5.25 V
最小供电电压	4.75 V	-	4.75 V	4.75 V	4.75 V	4.75 V
标称供电电压	5 V	-	5 V	5 V	5 V	5 V
表面贴装	YES	-	YES	YES	YES	YES
技术	CMOS	-	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	-	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子面层	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
端子形式	J BEND	-	GULL WING	GULL WING	GULL WING	GULL WING
端子节距	1.27 mm	-	0.65 mm	0.65 mm	0.65 mm	0.65 mm
端子位置	QUAD	-	QUAD	QUAD	QUAD	QUAD
处于峰值回流温度下的最长时间	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
宽度	29.3116 mm	-	14 mm	14 mm	14 mm	14 mm
uPs/uCs/外围集成电路类型	MEMORY CONTROLLER, DRAM	-	MEMORY CONTROLLER, DRAM	MEMORY CONTROLLER, DRAM	MEMORY CONTROLLER, DRAM	MEMORY CONTROLLER, DRAM