1 Megabit High Speed CMOS SRAM
DPS128M8CnY/BnY, DPS128X8CA3/BA3
DESCRIPTION:
The DPS128M8CnY/BnY, DPS128X8CA3/BA3 High Speed SRAM
devices are a revolutionary new memory subsystem using Dense-Pac
Microsystems’ ceramic Stackable Leadless Chip Carriers (SLCC).
Available in straight leaded, ‘’J’’ leaded or gullwing leaded packages,
or mounted on a 50-pin PGA co-fired ceramic substrate. These devices
pack 1-Megabits of low-power CMOS static RAM in an area as small
as 0.463 in
2
, while maintaining a total height as low as 0.082 inches.
The SLCC devices contain an individual 128K x 8 SRAMs, each
packaged in a hermetically sealed SLCC, making the modules suitable
for commercial, industrial and military applications.
The DPS128M8BnY/DPS128X8BA3 has one active low Chip Enable
(CE) while the DPS128M8CnY/DPS128X8CA3 has an active low Chip
Enable (CE) and an active high Select Line (SEL).
By using SLCCs, the ‘’Stack’’ family of modules offer a higher board
density of memory than available with conventional through-hole,
surface mount or hybrid techniques.
SLCC
‘’I’’ Leaded
SLCC
FEATURES:
•
•
•
•
•
•
•
•
Organization Available: 128Kx8
Access Times: 20*, 25, 30, 35, 45ns
Fully Static Operation - No clock or refresh required
Single +5V Power Supply,
±
10% Tolerance
TTL Compatible
Common Data Inputs and Outputs
Low Data Retention Voltage: 2.0V min.
Packages Available:
48 - Pin SLCC
48 - Pin Straight Leaded SLCC
48 - Pin ‘’J’’ Leaded SLCC
48 - Pin Gullwing Leaded SLCC
50 - Pin PGA Dense-Stack
‘’J’’ Leaded
SLCC
*
Commercial only.
Dense-Stack
Gullwing
Leaded SLCC
30A097-31
REV. D
This document contains information on a product that is currently released
to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
1
DPS128M8CnY/BnY, DPS128X8CA3/BA3
Dense-Pac Microsystems, Inc.
FUNCTIONAL BLOCK DIAGRAM
NOTE:
SEL apply to DPS128M8CnY/DPS128X8CA3 versions only.
PIN NAMES
A0 - A16
Address Inputs
I/O0 - I/O7
Data Input/Output
CE
Low Chip Enable
SEL
High Chip Enable
WE
Write Enable
OE
Output Enable
V
DD
Power (+5V)
V
SS
Ground
N.C.
No Connect
PIN-OUT DIAGRAM
48 - PIN LEADLESS STACK
48 - PIN STRAIGHT LEADED STACK
48 - PIN ‘’J’’ LEADED STACK
48 - PIN GULLWING LEADED STACK
50 - PIN PGA
DENSE-STACK
NOTE:
SEL apply to DPS128M8CnY/DPS128X8CA3 versions only, No Connect for DPS128M8BnY/DPS128X8BA3 versions.
2
30A097-31
REV. D
Dense-Pac Microsystems, Inc.
DPS128M8CnY/BnY, DPS128X8CA3/BA3
RECOMMENDED OPERATING RANGE
3
TRUTH TABLE
Mode
Not Selected
Not Selected
D
OUT
Disable
Read
Write
H = HIGH
Symbol
Characteristic
Min. Typ.
Max. Unit
V
DD
Supply Voltage
4.5 5.0
5.5
V
V
IH
Input HIGH Voltage 2.2
V
DD
+0.3 V
V
IL
Input LOW Voltage -0.5
2
0.8
V
M/B -55 +25 +125
Operating
o
T
A
I
-40 +25
+85
C
Temperature
C
0 +25
+70
SEL
L
X
H
H
H
CE
X
H
L
L
L
WE
X
X
H
H
L
Supply
OE I/O Pin Current
X High-Z Standby
X High-Z Standby
H High-Z Active
L
D
OUT
Active
X
D
IN
Active
X = Don’t Care
NOTE:
SEL applies to DPS128M8CnY/DPS128X8CA3 version only.
L = LOW
DC OUTPUT CHARACTERISTICS
Symbol
Parameter
V
OH
HIGH Voltage
V
OL
LOW Voltage
Conditions Min. Max. Unit
I
OH
= -4.0mA 2.4
V
I
OL
=8.0mA
0.4 V
CAPACITANCE
4
:
T
A
= 25°C, F = 1.0MHz
Symbol
Parameter
C
ADR
Address Input
C
CE
Chip Enable
C
SEL
Active High
Chip Select
C
WE
Write Enable
C
OE
Output Enable
C
I/O
Data Input/Output
Max.
10
10
10
10
10
14
Unit
Condition
ABSOLUTE MAXIMUM RATINGS
Symbol
T
STC
T
BIAS
V
DD
V
I/O
3
Parameter
Value
Storage Temperature
-65 to +150
Temperature Under Bias
-55 to +125
1
Supply Voltage
-0.5 to +7.0
1
Input/Output Voltage
-0.5 to V
DD
+0.5
Unit
°C
°C
°C
V
pF
V
IN2
= 0V
NOTE:
C
SEL
applies to DPS128M8CnY/DPS128X8CA3 version only.
DC OPERATING CHARACTERISTICS:
Over operating ranges
Symbol
I
IN
I
OUT
I
CC
I
SB1
I
SB2
I
DR3
I
DR2
V
OL
V
OH
Characteristics
Input
Leakage Current
Output
Leakage Current
Operating
Supply Current
Full Standby
Supply Current
Standby Current (TTL)
Data Retention
Supply Current
(3.0V)
Data Retention
Supply Current
(2.0V)
Output Low Voltage
Output High Voltage
o
Test Conditions
V
IN
= 0V to V
DD
V
I/O
= 0V to V
DD
,
CE or OE = V
IH
, or WE = V
IL
Cycle=min., Duty=100%
I
OUT
= 0mA
V
IN
≥
V
DD
-0.2V or
V
IN
≤
V
SS
+0.2V
CE = V
IH
V
DR
= 3.0V, CE
≥
V
DR
-0.2V,
(or SEL
≤
0.2V, V
IN
≥
V
DD
-0.2V
or V
IN
≤
+0.2V)
V
DR
= 2.0V, CE
≥
V
DR
-0.2V,
(or SEL
≤
0.2V, V
IN
≥
V
DD
-0.2V
or V
IN
≤
+0.2V)
I
OUT
= 8.0mA
I
OUT
= -4.0mA
Typ.
(†)
-
-
100
0.4
25
70
35
-
-
C
Min.
Max.
Min.
I
Max.
M/B
Min.
Max.
Unit
µA
µA
mA
mA
mA
µA
µA
V
V
-5
-10
+5
+10
140
5
30
400
250
0.4
-5
-10
+5
+10
140
5
35
600
400
0.4
-5
-10
+5
+10
160
10
35
2000
1800
0.4
2.4
2.4
2.4
† Typical measurements made at +25 C, Cycle = min., V
DD
= 5.0V.
NOTE:
Test Conditions in parenthesis apply to DPS128M8CnY/DPS128X8CA3 version only.
30A097-31
REV. D
3
DPS128M8CnY/BnY, DPS128X8CA3/BA3
AC TEST CONDITIONS
Input Pulse Levels
Input Pulse Rise and Fall Times
Input and Output Timing Reference Levels
0V to 3.0V
5ns
1.5V
Dense-Pac Microsystems, Inc.
Figure 1.
Output Load
* Including Probe and Jig Capacitance.
+5V
480Ω
OUTPUT LOAD
Load
1
2
C
L
100pF
5pF
Parameters Measured
except t
LZ1
, t
LZ2
, t
HZ1
, t
HZ2
, t
OHZ
, t
OLZ
, and t
WHZ
t
LZ1
, t
LZ2
, t
HZ1
, t
HZ2
, t
OHZ
, t
OLZ
, and t
WHZ
D
OUT
C
L
*
255Ω
NOTE:
t
LZ2
and t
HZ2
apply to DPS128M8CnY/DPS128X8CA3 version only.
Data Retention AC Characteristics
Symbol
V
DR
V
CDR
t
R
Parameter
V
DD
for Data
Retention
Chip Disable to
Data Retention Time
Operation Recovery Time
Test Conditions
CE
≥
V
DR
-0.2V, (SEL
≥
V
DR
-0.2V,
or V
IN
≤
V
DR
-0.2V or V
IN
≤
0.2V)
See Data Retention Waveform
See Data Retention Waveform
8
Min.
2.0
0
5
Typ.
-
-
-
Max.
-
-
-
Unit
V
ns
ms
NOTE:
Test Conditions in parenthesis apply to DPS128M8CnY/DPS128X8CA3 version only.
DATA RETENTION WAVEFORM:
CE Controlled.
V
DD
4.5V
2.3V
V
DR1
CE
0V
CE
≥
V
DD
-0.2V
DATA RETENTION WAVEFORM:
SEL Controlled. (Applies to DPS128M8CnY/DPS128X8CA3 only)
V
DD
4.5V
SEL
V
DR2
0.4V
0V
SEL
≤
-0.2V
4
30A097-31
REV. D
Dense-Pac Microsystems, Inc.
DPS128M8CnY/BnY, DPS128X8CA3/BA3
AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE:
Over operating ranges
No. Symbol
1
2
3
4
5
6
7
8
9
10
11
12
t
RC
t
AA
t
CO1
t
CO2
t
OE
t
LZ1
t
LZ2
t
OLZ
t
HZ1
t
HZ2
t
OHZ
t
OH
Parameter
Read Cycle Time
Address Access Time
CE to Output Valid
SEL to Output Valid
Output Enable to Output Valid
CE to Output in LOW-Z
4, 5
SEL to Output in LOW-Z
4, 5
Output Enable to Output in LOW-Z
4, 5
CE to Output in HIGH-Z
4, 5
SEL to Output in HIGH-Z
4, 5
Output Enable to Output in HIGH-Z
4, 5
Output Hold from Address Change
20ns*
Min.
Max.
25ns
Min.
Max.
30ns
Min.
Max.
35ns
Min.
Max.
45ns
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
20
20
8
3
3
0
10
10
8
3
25
25
25
25
10
3
3
0
12
12
10
3
30
30
30
30
15
3
3
0
15
15
15
3
35
35
35
35
20
3
3
0
20
20
20
3
45
45
45
45
25
3
3
0
25
25
25
3
* Available in Commercial Only.
NOTE:
t
CO2
, t
LZ2
and t
HZ2
apply to DPS128M8CnY/DPS128X8CA3 version only.
READ CYCLE
ADDRESS
CE
SEL
OE
DATA I/O
NOTE:
SEL, t
CO2
, t
LZ2
and t
HZ2
apply to DPS128M8CnY/DPS128X8CA3 version only.
WAVEFORM KEY
Data Valid
Transition from
HIGH to LOW
Transition from
LOW to HIGH
Data Undefined
or Don’t Care
30A097-31
REV. D
5
Altera SoC
