DR-11525
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®
16-BIT HIGH FREQUENCY HYBRID
DIGITAL-TO-RESOLVER CONVERTER
FEATURES
•
Accuracy Up to 1 Minute
•
Operational Up to 10 kHz
•
2 Vrms, 6.81 Vrms, 11.8 V
L
-
L
, or
Scalable Resolver Outputs
•
2 mA rms Output
•
16-Bit Resolution
•
8-Bit/2-Byte Double Buffered
Transparent Latches
•
DC-Coupled Reference Accepts Any
Waveform
•
High-Rel CMOS D/R Chip
DESCRIPTION
The DR-11525 is a versatile multiplying Digital-to-Resolver converter.
The digital input represents an angle, and the output is resolver type,
SIN/COS. The reference input will accept any waveform, even a saw-
tooth for CRT drive. Because the reference is DC-coupled to the out-
put, the DR-11525 can be used as: a Digital-to-Resolver converter
using a sinusoidal reference as an input; a Digital-to-SIN/COS DC
converter using a DC reference; a polar-to-rectangular converter
using a reference input proportional to the radius vector; or a rotating
cartwheel sweep generator for PPI displays using a sawtooth refer-
ence.
The DR-11525 is a complete Digital-to-Resolver (D/R) converter in
one hybrid module. The DR-11525 circuit design allows for higher
accuracy and reduces the output scale factor variation so that the out-
put can drive displays directly. The output line-to-ground voltage can
be scaled by external resistors. The DR-11525 also includes high AC
and DC common-mode rejection at the reference input.
•
No +5 V Supply Required
APPLICATIONS
Because of its high reliability, small size and low power consumption,
the hybrid DR-11525 is ideal for the most stringent and severe indus-
trial and military ground or avionics applications. All units are avail-
able with MIL-PRF-38534 processing as a standard option.
Among the many possible applications are computer-based systems
in which digital angle information is processed, such as
synchro/resolver simulators, flight trainers, flight instrumentation, fire
control systems, IR, and radar and navigation systems. In addition,
the DR-11525 is ideal for motor and robotic control test systems.
FOR MORE INFORMATION CONTACT:
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
Technical Support:
1-800-DDC-5757 ext. 7771
©
1996, 1999 Data Device Corporation
Data Device Corporation
www.ddc-web.com
TEST POINT - R
13.37 k
D/R CONVERTER
13.37 k
36.71 k
49.92 k
HIGH ACCURACY
LOW SCALE FACTOR
VARIATION
+C
S2
RESOLVER SCALING
OUTPUT AMPLIFIERS
REFERENCE
CONDITIONER
BITS 1-16
+S
S1
36.71 k
49.92 k
RESOLVER
OUTPUTS
S3
S4
TRANSPARENT
LATCH
TRANSPARENT
LATCH
LA
LM
BITS 1-8
BITS 9-16
DIGITAL INPUT
LL
REFERENCE INPUTS
DIFFERENTIAL
(NOTE 1)
26 V
2
SINGLE-ENDED
(NOTE 2)
26 V
ADJUSTABLE
(NOTE 3)
4.4 V
NOTES: 1) 26 VRMS REFERENCE IN = 11.8 V
L-L
DIFFERENTIAL OUTPUT
2) 26 VRMS REFERENCE IN = 6.81 VRMS SINGLE-ENDED OUTPUT
3) 4.4 VRMS REFERENCE IN = 2 VRMS SINGLE-ENDED OUTPUT
DR-11525
G-06/05-0
FIGURE 1. DR-11525 BLOCK DIAGRAM
TABLE 1. DR-11525 SPECIFICATIONS
Apply over temperature range, power supply range, reference voltage
and frequency range, and 10% harmonic distortion in the reference.
UNIT
VALUE
PARAMETER
RESOLUTION
Bits
16
ACCURACY AND
DYNAMICS
Output Accuracy
Minutes 4 to 1 min. (See Ordering information)
1 minute part: 1 min up to 1 kHz,
1.5 min for 1 to 5 kHz, and 3 min for
5 to 10 kHz (guaranteed by design -
tested at 5 kHz)
Differential Linearity
LSB ±1 max
Output Settling Time
µsec
Less than 20 for any digital step change
DIGITAL INPUT
Natural binary angle, parallel positive
Logic Type
logic CMOS and TTL compatible.
Inputs are CMOS transient protected.
Logic 0 = 0 to +1 V
Logic 1 = +2.2V to +5V
µA
20 max to GND (bits 1-16)
Load Current
20 max to +5V (LL, LM, LA)
See Timing Diagram (FIGURE 2.).
REFERENCE INPUT
Three differential solid-state inputs: two
Type
for standard 26V, one programmable.
Hz
DC to 10k
Frequency Range
Standard Input
Voltage
(Note 1)
RH3-RL3
RH2-RL2
RH-RL
INTRODUCTION
As shown in FIGURE 1, the signal conversion in the DR-11525
is performed by a high-accuracy digital-to-resolver converter
whose sin and cos outputs have a low scale factor variation as a
function of the digital input angle. This resolver output is ampli-
fied by scaling amplifiers for resolver output. The output line cur-
rents can be 2 mA rms max, which is sufficient for driving R/D
converters, solid-state control transformers, and displays. Output
power amplifiers will be required, however, for driving electro-
mechanical devices such as synchros and resolvers.
The reference conditioner has a differential input with high AC
and DC common mode rejection, so that a reference isolation
transformer will seldom be required. There are three sets of ref-
erence inputs which provide three different input/output ratios.
The RH- RL input provides a 0.45 ratio between the reference
input and the signal output and is designed to provide 11.8 VL-L
differential output for a 26 Vrms reference input. The RH2-RL2
input provides a 0.52 ratio between the reference input and the
signal output and is designed to provide a 6.81 Vrms single-
ended output for a 26 Vrms reference input. The RH3-RL3 input
provides a 0.91 ratio between the reference input and the signal
output and is designed to provide a 2 Vrms single-ended output
for a 4.4 Vrms reference input. Series resistors can be added to
accommodate higher reference levels or to reduce the output
level.
V
V
V
4.4
26
26
100 ±0.5%
200 ±0.5%
Resolver
2 max
(Tracks Reference Input Voltage)
11.8 nominal
6.81 (single ended)
2.0 nominal (single ended)
±0.5 max
±0.1 max
±15 max Varies with input angle.
INPUT IMPEDANCE
k ohm
Single-Ended: RH-gnd
k ohm
Differential: RH to RL
ANALOG OUTPUT
Type
mA rms
Output Current
Standard Output
Voltage
(Note 2)
Vrms
L-L
RH-RL
RH2-RL2
Vrms
RH3-RL3
Vrms
Transform. Ratio Tol.
%
Scale Factor Variation
%
DC Offset (Single ended)
mV
TABLE 2. ANGLES IN DEGREES
CROSS REFERENCED TO A 16-BIT DIGITAL WORD
DEGREES
(HEX)
1
0° (0000)
15° (0AAB)
30° (1555)
45° (2000)
60° (2AAB)
75° (3666)
90° (4000)
120°
135°
180°
240°
270°
285°
300°
(5555)
(6000)
(8000)
(AAAB)
(C000)
(CAAB)
(D555)
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
Φ
16 BIT DIGITAL WORD (Φ) (1 = MSB, 16 = LSB)
2 3 4
0 0 0
0
0
1
1
1
0
1 0
1 0
1 1
0 0
0 1
1 0
1 0
1 0
0
1
1
0
1 1
1 1
1 1
0
0
0
0
0
0
1
0
0
1
0
1
0
0
0
0
0
1
0
1
0
1
1
5
0
1
0
0
1
0
1
0
0
0
0
1
0
1
0
0
1
1
0
1
6
0
0
1
0
0
1
1
0
1
0
0
0
0
0
1
0
1
0
1
1
7
0
1
0
0
1
0
1
0
0
0
0
1
0
1
0
0
1
1
0
1
8
0
0
1
0
0
1
0
1
0
0
0
0
0
1
0
1
0
1
1
9 10
11 12
13 14
1
5 16
0
1
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
1
1
0
1
0
0
1
0
0
1
0
1
0
0
0
0
0
1
1
0
0
1
1
0 0
1
0
0
1
0
1
0
0
0
0
1
0
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
0
1
0
0
1
0
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1 1
0 1
0 0
1 1
0
1
1
0 0
0 1
0 0
0 0
1 1
0 0
1 1
0 1
0
1
1
0
1 1
0 1
1 1
POWER SUPPLIES
-15 ±5%
Voltage
V
+15 ±5%
-18V
Max volt. w/o damage
+18V
Current or Impedance
mAmax 35+ load current 35+ load current
TEMPERATURE
RANGES (CASE)
Operation
°C
-55 to +125
-1 Option
°C
-40 to +85
-2 Option
°C
0 to +70
-3 Option
°C
-55 to +135
Storage
PHYSICAL
CHARACTERISTICS
36-pin DDIP
Package Type
in.(mm) 0.78 x 1.9 x 0.21 (19.7 x 48.1 x 5.3)
Size
oz (g)
0.85 (24)
Weight
Notes: 1) Maximum reference input RH-RL = 26V +10%; RH2-RL2 = 26V
+10%; RH3-RL3 = 16.4V. (2) Minimum voltage output (when using scalable ref-
erence input) is 1V differential or 0.5V single ended. (3) Differential is line-to-line
(L-L); single ended is line-to-ground (L-gnd).
315° (E000)
330° (EAAB)
345° (F555)
359° (FFFF)
0 0
0 0
0 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
Data Device Corporation
www.ddc-web.com
3
DR-11525
G-06/05-0
POWER SUPPLY CYCLING
Power supply cycling of the DDC converter should follow the
guidelines below to avoid any potential problems. Strictly main-
tain proper sequencing of supplies and signals per typical
CMOS circuit guidelines:
- Apply power supplies first (+15, -15V and ground).
- Apply digital control signals next.
- Apply analog signals last.
The reverse sequence should be followed during power down
of the circuit.
200 nS min.
TRANSPARENT
LATCHED
DATA 1-16 BITS
50 nS min.
100 nS min.
Data Changing
Data Stable
FIGURE 2A. LL, LM, LA TIMING DIAGRAMS (16 BIT)
LA
200 nS min.
200 nS min.
LM
Bits (1-8)
200 nS min.
LL
Bits (9-16)
DATA
50 nS min.
100 nS min.
50 nS min.
100 nS min.
LA, LM, LL
Transparent = Hi
Latched = Lo
Data Changing
Data Stable
FIGURE 2B. LL, LM, LA TIMING DIAGRAMS (8 BIT)
Data Device Corporation
www.ddc-web.com
4
DR-11525
G-06/05-0
The reference conditioner output -R is intended for test purpos-
es. For a 26 Vrms nominal input to RH, RL, -R should be 5.9
Vrms.
The timing relationship of LL, LM, and LA is shown in FIGURE 2
as a design reference.
OUTPUT PHASING AND OUTPUT SCALE FACTOR
The analog output signals have the following phasing:
Resolver output:
S3—S1 = (RH - RL)Ao(1 + A(θ)) sin
θ
S2—S4 = (RH - RL)Ao(1 + A(θ)) cos
θ
OUTPUT SCALING AND REF. LEVEL ADJUSTMENT
The DR-11525 operates like a multiplying D/A converter in that
the voltage of each output line is directly proportional to the ref-
erence voltage. See FIGURE 3.
The magnitude of the resistors, R', in ohms is calculated as fol-
lows:
*Note: For RH2, RL2 and RH3, RL3: Vout(single-ended) = 1/2 Vout
L-L
.
The output amplifiers simultaneously track reference voltage
fluctuations because they are proportional to (RH - RL). The
transformation ratio Ao is 11.8/26 for 11.8 Vrms
L-L
output. The
maximum variation in Ao from all causes is ± 0.2%. The term
A(θ) represents the variation of the amplitude with the digital sig-
nal input angle. A(θ), which is called the scale factor variation, is
a smooth function of (θ) without discontinuities and is less than
±0.1% for all values of (θ). Therefore, the analog output can vary
as much as ±0.3% due to the transformation ratio and scale fac-
tor variations.
Because the amplitude factor (RH - RL)Ao(1 + A(θ)) varies
simultaneously on all output lines, it will not be a source of error
when the DR-11525 is to drive a ratiometric system such as a
synchro or resolver. However, if the outputs are used indepen-
dently, as in x-y plotters, the amplitude variations must be taken
into account.
For RH-RL:
Vout
L-L
Vin
=
45.38k
100k + R'
45.38k
86.63k + R'
45.38k
49.92k + R'
PIN
1
2
3
4
5
6
7
8
9
10
11
12
*For RH2-RL2: Vout
L-L
Vin
*For RH3-RL3: Vout
L-L
Vin
=
=
TABLE 3. PIN CONNECTION TABLE
NAME
NC
+15V
GND
-15V
RH2 (6.81V)
RL2 (6.81V)
-R
RL (11.8V)
RL3 (2V)
RH (11.8V)
RH3 (2V)
Bit 14
PIN
13
14
15
16
17
18
19
20
21
22
23
24
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
NAME
13
12
11
10
9
8
7
6
5
4
3
2
PIN
25
26
27
28
29
30
31
32
33
34
35
36
NAME
Bit 1 (MSB)
Bit 15
Bit 16 (LSB)
LM
LL
LA
S4 (-COS)
S1 (-SIN)
NC
NC
S3 (+SIN)
S2 (+COS)
REFERENCE
INPUTS
13.37k
36.71k
49.92k
45.38k
_
1) 26V
V (RH-RL)
13.37k
36.71k
49.92k
+
VOUT L-L
1) 11.8V Nom
2) 6.8V Single Ended
8.703k
3) 2.0V Nom
2) 26V
V (RH2-RL2)
R′
3) 4.4V
V (RH3-RL3)
R′
*Changing input volt, will scale down output volt
FIGURE 3. REFERENCE LEVEL ADJUSTMENT
35
32
36
31
Notes:
1. -R (Pin 7) can be used for test purposes to detect whether a reference signal
is present. See block diagram.
2. Functions LL, LA, and LM may be left unconnected when not used.
3. External scaling resistor pin 11 RH3 output pins (31, 32, 35, 36).
4. RH and RL (pins 10, 8) 26 V reference with differential outputs on pins 35, 36,
32, 31.
5. RH2 and RL2 (pins 5, 6) 26 V reference with single-ended output on pins 35,
36.
6. RH3 and RL3 (pins 11, 9) 4.4 V reference with single-ended outputs on pins
35, 36.
35
(+SIN)
S3
S1
DR-11525
S2
S4
S3
S1
DR-11525
S2
S4
S3
S3
S2
36
(+COS)
S2
GND 3
FIGURE 4. DIFFERENTIAL RESOLVER OUTPUT
Data Device Corporation
www.ddc-web.com
5
FIGURE 5. SINGLE-ENDED RESOLVER OUTPUT
DR-11525
G-06/05-0
嵌入式系统
