DR-11800
16-BIT DIGITAL-TO-RESOLVER CONVERTER
DESCRIPTION
The DR-11800 is a small size, high
accuracy, 16-bit digital-to-sine/cosine
converter. Available in accuracies up
to 1 arc minute, the DR-11800 is con-
tained in a 28-pin, one-square-inch
hermetically sealed package and
requires +15 Vdc and -15 Vdc power
supplies. The reference conditioner
allows for either 115 Vrms or 26 Vrms
reference input for a 6.8 Vrms sin/cos
output. Two registers for the input of
the 16-bit (CMOS/TTL) natural binary
angle data allow for compatibility with
an 8-bit or 16-bit data bus.
Internally, the DR-11800 has a multi-
plying digital-to-sin/cos converter
made of two function generators and
a quadrant select network. Quadrant
information is available from the two
most significant bits. The two function
generators use the remaining angular
data along with the buffered reference
voltage. Similar to a multiplying DAC
(digital-to-analog converter), the DR-
11800 uses high accuracy resistive
ladder networks and solid state
switching to control the attenuation of
the reference voltage. The output
buffer amplifiers allow for up to 2 mA
output drive.
FEATURES
•
28-Pin Square Package
•
1 Arc Minute Accuracy
•
0.03% Radius Accuracy
•
Microprocessor Compatible -
8- and 16-Bit
APPLICATIONS
High accuracy, high reliability, small
size, low power consumption and
MIL-PRF-38534 processing avail-
ability, make the DR-11800 suitable
for industrial and military ground or
avionics applications. Possible appli-
cations include digital remote posi-
tioning, resolver angle simulators,
flight trainer, flight instrumentation,
radar and navigational systems, and
PPI displays including moving target
indicators. Other applications are syn-
chro/resolver system development
and test, and wraparound test of syn-
chro/resolver-to-digital converters.
•
Double-Buffered Inputs
•
Pin-Programmable Reference
Input (for 26 and 115 Vrms)
•
DC-Coupled Reference and
Outputs
•
Requires Only ±15 V Power
Supplies
•
TTL and CMOS Compatible
•
Pin-for-Pin Replacement for
Natel’s HDR2406
+V
S
24
–V
S
25
HBE 9
(MSB) B1 1
B2 2
B3 3
B4 4
B5 5
B6 6
INPUT BUFFERS
B7 7
B8 8
16-BIT
HOLDING
REGISTER
16-BIT
HIGH
ACCURACY
MULTIPLYING
DIGITAL
TO SIN / COS
CONVERTER
8-BIT
INPUT
REGISTER
D
CK
Q1
(MSB
BIT 1)
28 SINθ
B9 11
B10 12
B11 13
B12 14
B13 15
B14 16
B15 17
(LSB) B16 18
BUFFER
AMPLIFIERS
20 COSθ
8-BIT
INPUT
REGISTER
D
Q16
CK
CK PE
BIT 16
(LSB)
LBE 10
LDC 19
-
+
REFERENCE
CONDITIONER
23
GND
21
27
22
RL26 RH115 RL115
26
RH26
FIGURE 1. DR-11800 BLOCK DIAGRAM
©
1996, 1999 Data Device Corporation
TABLE 1. DR-11800 SPECIFICATIONS
PARAMETER
VALUE
REMARKS
DIGITAL ANGULAR
Resolution
16 Bits
Bit 1 = MSB, Bit 16 = LSB
Accuracy
±4 arc-minutes
Accuracy applies over
±2 arc-minutes
operating temperature
±1 arc-minutes
range.
SCALE FACTOR
VARIATION
Scale Factor Variation
TABLE 1. DR-11800 SPECIFICATIONS (CONTINUED)
PARAMETER
VALUE
REMARKS
REGISTER CONTROLS
(Continued)
200
ηsec
min
Before data transfer.
Data Set-up Time
Data Hold Time
Before input data
200
ηsec
min
changes.
POWER SUPPLIES
Supply Voltages (±Vs)
Supply Current
Supply Rejection
TEMPEATURE RANGES
Operating Case
-3XXX and -8XXX
-1XXX and -4XXX
Storage
PHYSICAL
CHARACTERISTICS
Type
Size
Weight
±15 V dc ±10%
±35 mA max
70 db
Without output clip-
ping.
Typ.
±0.1% max
Simultaneous ampli-
tude variation in both
outputs as a function
of digital angle.
REFERENCE INPUT
(RH-RL)
Voltage
Frequency Range
Input Resistance
ANALOG OUTPUTS
Max SIN
θ,
COS
θ
115 V rms or
26 V rms
dc to 1000 Hz
Differential solid-state
input.
0°C to +70°C
-55°C to +125°C
-65°C to +135°C
Differential 230 kΩ 115 V rms reference
Differential 52 kΩ 26 V rms reference
6.8 V rms, ±1.5 %
Output voltage varies
in direct proportion to
reference voltage.
Op amp output.
28 Pin Square
1.0 x 1.0 x 0.21 in.
(25 x 25 x 5.3) mm
0.6 oz
(17 g) max
Twice Normal Voltage
±18 V dc
-0.3 V dc to +6.5 V dc
Output Current
Output Impedance
Zero Offset (dc)
Offset Drift
Output Settling Time
2 mA rms
<
1 ohm
±10 mV typical
±25 mV max
25
µV/°C
typical,
50
µV/°C
max
50
µsec
max to
accuracy of con-
verter.
ABSOLUTE MAXIMUM RATINGS
Reference Input:
Power Supply Voltage (±Vs):
Digital Inputs:
NOTE. Although digital inputs are CMOS protected, storage in conductive foam
is recommended.
For any digital step
change.
DIGITAL INPUTS
Logic Levels
Logic 0
Logic 1
Loading
Input Current
Data Bits (B1-B16)
HBE, LBE, LDC
-0.3 Vdc to 0.8 V dc
2.4 Vdc to 5.5 V dc
0.1 TTL load
No external logic volt-
ages required.
CMOS transient pro-
tected.
15
µA
typ, “active” For less than 16 bits,
unused pins can float.
pull-down to gnd
-15
µA
typ, “active” Unused pins can float.
pull-up to internal
logic supply
Logic 1
’
Logic 0
8 MSBs enter high
byte input register.
High byte register
remains unaffected.
8 LSBs enter low byte
input register.
Low byte register
remains unaffected
Data from input regis-
ters transferred to
holding register.
Data in holding regis-
ter remains unaffected
For guaranteed data
transfer.
REGISTER CONTROLS
HBE
LBE
Logic 1
Logic 0
LDC
Logic 1
Logic 0
600
ηsec
min
Pulse Width
2
ANALOG OUTPUT PHASING
The DR-11800 provides an output of 6.8V sinθ and 6.8V cosθ
for either a 26 Vrms reference (use pin 26; RH26, and pin 22;
RL26) or 115 Vrms reference (use pin 21; RH115, and pin 27;
RL115). FIGURE 2 illustrates the input connection for a 26V or
115V reference. FIGURE 3 illustrates the output phasing.
DIGITAL INTERFACE
The DR-11800 has double-buffered input registers which allow
for easy implementation of an interface with 8-bit or 16-bit data
buses. The DR-11800 can also be set up for asynchronous data
inputs. If the LBE, HBE and LDC input pins are left open, the
internal pull-up circuitry will set these pins to a high state and the
information at the data inputs (B1-B16) will be continuously con-
verted to sinθ and cosθ at the analog outputs. In applications
requiring less than 16-bit resolution, the unused pins can be left
open. The data bits (B1-B16) are internally pulled-down to apply
a logic 0 to unconnected data inputs.
+VS –VS
RL 26 22
21
RH 115
RL 115 27
+VS –VS
RL 26 22
N/C
26 V
REFERENCE
N/C
RH 115 21
RL115
RH26
27
26
N/C
SIN
θ
COS
θ
115 V
REFERENCE
SIN
θ
COS
θ
N/C RH 26
26
16-BIT ANGULAR DATA
16-BIT ANGULAR DATA
HBE
HBE
LBE
LDC
GND
LBE
LDC
GND
NOTE: N/C NO CONNECTION
FIGURE 2. CONNECTIONS TO 26 V/115 V REFERENCE
Vmax
SIN
θ
IN PHASE
WITH VIN
0˚
90
180
270
360˚
θ
DEGREES
-Vmax
SIN OUTPUT = 6.8V rms(1+n)SIN
θ
COS OUTPUT = 6.8V rms(1+n)COS
θ
n IS THE SCALE FACTOR VARIATION AS A
FUNCTION OF DIGITAL ANGLE(±
0.1%)
COS
θ
FIGURE 3. OUTPUT PHASING
3
DATA TRANSFER FROM AN 8-BIT DATA BUS
Applications with an 8-bit data bus require two-byte loading of
the digital input (see FIGURE 4).
FIGURE 5 shows the timing for two-byte data transfers.
1. LDC is low (logic 0) so that the contents of the holding regis-
ter are latched and will remain unaffected by the changes on the
input registers.
2.When the LBE is set high (logic 1) the 8 LSBs (B9-B16) are
transferred to the low byte. The LBE must remain high for a min-
imum of 800 nsec after the data is stable. The data should
remain stable for 200 nsec after the LBE is set low (logic 0).
3.When the HBE is set high (logic 1) the 8 MSBs (B1-B8) are
transferred to the low byte. The HBE must remain high for a min-
imum of 800 nsec after the data is stable. The data should
remain stable for 200 nsec after the HBE is set low (logic 0).
4.When the LDC is set high (logic 1) the data is transferred from
the two input registers to the holding register. The LDC should
be held high for 600 nsec minimum. Once the LDC is set low,
the cycle can begin again.
Note: LBE, HBE, and LDC are level-actuated functions.
DATA TRANSFER FROM A 16-BIT DATA BUS
Applications interfacing with a 16-bit data bus require only single
byte loading, as shown in FIGURE 6. LBE and HBE are either
unconnected or tied together and pulsed high to load data.
As shown in the timing diagram (see FIGURE 7) 200 nsec after
the data is stable the LDC is set high (logic 1) to transfer the data
to the holding register. Since LDC is level actuated, it must
remain high for the time specified (600 nsec) to transfer the data.
8 LSBs TRANSFERRED
TO INPUT REGISTERS
DATA
CHANGING
DATA
DATA SET UP
200 ns
MIN
8 MSBs TRANSFERRED
TO INPUT REGISTERS
DATA
STEADY
(LSBs)
(MSBs)
LBE
PULSE
WIDTH
600 ns
MIN
DATA HOLD
200ns
MIN
HBE
600 ns
MIN
600ns
MIN
LDC
PULSE
WIDTH
DATA TRANSFERRED TO
HOLDING REGISTERS
1
2
3
4
5
6
DATA BUS
7
8
DR-11800
11
12
13
14
15
16
17
18
HBE
LBE
LBE
HBE
LDC
LOAD LSBs
LOAD MSBs
LOAD
CONVERTER
FIGURE 5. TIMING FOR 8-BIT BUS TRANSFER
(MSB)
D7
D6
D5
D4
D3
D2
D1
D0
(MSB)
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
(LSB)
1
2
3
4
5
6
7
8
11
12
13
14
15
16
17
18
19
LDC
LOAD
CONVERTER
10
9
LBE
HBE
NOT CONNECTED
OR LOAD DATA PULSE
DR-11800
(LSB)
FIGURE 4. DATA TRANSFER FROM 8-BIT BUS
4
FIGURE 6. DATA TRANSFER FROM 16-BIT BUS
DIGITAL-TO-RESOLVER/SYNCHRO CONVERTERS
The DR-11800 provides single-ended sin/cos outputs.
FIGURE 8 shows the DR-11800 connected as a 4-Wire Digital-
to-Resolver Converter (S1, S2, S3, and S4) using external Power
Amplifiers and transformers.
FIGURE 9 shows the DR-11800 connected as a 3-Wire Digital-
to-Synchro Converter (S1, S2, and S3) using external Power
Amplifiers and transformers.
200 ns
MIN
DATA TRANSFERRED
TO INPUT REGISTERS
DATA
CHANGING
DATA
DATA
STEADY
ALL 16 BITS
200 ns
MIN
HBE LBE
POWER SUPPLY DECOUPLING
Decoupling capacitors are recommended on the
+Vs
and
-Vs
supplies. A 1
µ
F tantalum capacitor in parallel with a 0.01
µ
F
ceramic capacitor should be mounted as close to the supply as
possible.
DATA TRANSFERRED TO
HOLDING REGISTERS
600 ns
MIN
600 ns
MIN
LDC
FIGURE 7. TIMING FOR 16-BIT BUS TRANSFER
RH
RL
1:n
RH
SIN
θ
1:N
S1
S3
DR-11800
RH
RL
1:n
RH
RL
28
P.A.
RL
28
SIN
θ
1:N
P.A.
S1
S3
DR-11800
1:
√
3 N
2
S2
20
COS
θ
P.A.
1:N
S4
S2
20
16-BIT ANGULAR DATA
COS
θ
P.A.
16-BIT ANGULAR DATA
FIGURE 8. 4-WIRE DIGITAL-TO-RESOLVER CONVERTER
5
FIGURE 9. 3-WIRE DIGITAL-TO-SYNCHRO CONVERTER
嵌入式系统
