DS1007
7-1 Silicon Delay Line
www.dalsemi.com
FEATURES
PIN ASSIGNMENT
All-silicon time delay
IN1
1
16
IN3
7 independent buffered delays
OUT1
2
15
OUT3
Delay tolerance ±2 ns
Four delays can be custom set between 3 ns
IN4
IN2
3
14
IN3
IN1
1
16
and 10 ns
OUT2
4
13
OUT4
OUT3
OUT1
15
2
Three delays can be custom set between 9 ns
14
3
IN4
IN2
V
CC
5
12
GND
and 40 ns
OUT4
4
OUT2
13
OUT7
11
IN5
6
5
GND
V
CC
12
Delays are stable and precise
OUT7
6
11
IN5
OUT5
7
10
Economical
IN7
7
IN7
10
OUT5
Auto-insertable, low profile
9
IN6
8
OUT6
IN6
8
OUT6
9
Surface mount 16-pin SOIC
DS1007 16-Pin DIP (300-mil)
DS1007S 16-Pin SOIC
Low-power CMOS
See Mech. Drawings Section
(300-mil)
TTL/CMOS-compatible
See Mech. Drawings Section
Vapor phase, IR and wave solderable
Custom specifications available
PIN DESCRIPTION
Quick turn prototypes
IN1 - IN7
- Inputs
Out1 – Out7 - Outputs
GND
- Ground
V
CC
- +5 Volts
DESCRIPTION
The DS1007 7-in-1 Silicon Delay Line provides seven independent delay times which are set by Dallas
Semiconductor to the customer’s specification. The delay times can be set from 3 ns to 40 ns with an
accuracy of
±2
ns at room temperature. The device is offered in both a 16-pin DIP and a 16-pin SOIC.
Since the DS1007 is an all-silicon solution, better economy and reliability are achieved when compared to
older methods using hybrid technology. The DS1007 reproduces the input logic state at the output after
the fixed delay. Dallas Semiconductor can customize standard products to meet special needs. For special
requests and rapid delivery, call (972) 371–4348.
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DS1007
LOGIC DIAGRAM
Figure 1
PART NUMBER DELAY TABLE (t
PLH
)
Table 1
PART #
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
DS1007-1
3ns
4ns
5ns
6ns
9ns
13ns
18ns
DS1007-2
4
6
8
10
12
14
16
DS1007-3
3
3
3
3
10
10
10
DS1007-4
4
4
4
4
12
12
12
DS1007-5
5
5
5
5
15
15
15
DS1007-6
6
6
6
6
20
20
20
DS1007-7
7
7
7
7
25
25
25
DS1007-8
8
8
8
8
30
30
30
DS1007-9
9
9
9
9
35
35
35
DS1007-10
10
10
10
10
40
40
40
DS1007-11
3
4
6
8
10
12
14
DS1007-12
3
4
6
8
10
15
20
DS1007-13
3
4
6
8
12
15
20
DS1007-14
7
7
7
7
9
9
9
Custom delays available. Out 1 through Out 4 can be custom set from 3 to 10 ns (leading edge only
accuracy). Out 5 through Out 7 can be set from 9 to 40 ns (both leading and trailing edge accuracy).
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DS1007
TIMING DIAGRAM: SILICON DELAY LINE
Figure 2
TEST CIRCUIT
Figure 3
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DS1007
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
Short Circuit Output Current
-1.0V to +7.0V
0°C to 70°C
-55°C to +125°C
260°C for 10 seconds
50 mA for 1 second
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS
PARAMETER
Supply Voltage
High Level Input
Voltage
Low Level Input
Voltage
Input Leakage
Current
Active Current
High Level Output
Current
Low Level Output
Current
SYM
V
CC
V
IH
V
IL
I
I
I
CC
I
OH
I
OL
0.0V
≤
V
I
≤
V
CC
V
CC
=Max;
Period=Min.
V
CC
=Min.
V
OH
=2.4V
V
CC
=Min.
V
OL
=0.5V
TEST
CONDITION
MIN
4.75
2.2
-0.5
-1.0
(0°C to 70°C; V
CC
= 5.0V ± 5%)
TYP
5.00
MAX
5.25
V
CC
+ 0.5
0.8
1.0
40.0
70.0
-1.0
12.0
UNITS
V
V
V
uA
mA
mA
mA
2
NOTES
1
1
1
AC ELECTRICAL CHARACTERISTICS
PARAMETER
Input Pulse Width
Input to Output
(leading edge)
Power-up Time
SYMBOL
t
WI
t
PLH
t
PU
Period
MIN
100% of t
PLH
(T
A
= 25°C; V
CC
= 5V ± 5%)
TYP
Table 1
100
MAX
UNITS
ns
ns
ms
ns
NOTES
3, 4, 5
7
6
3 (t
WI
)
CAPACITANCE
PARAMETER
Input Capacitance
SYMBOL
C
IN
MIN
TYP
5
MAX
10
(T
A
= 25°C)
UNITS
pF
NOTES
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DS1007
NOTES:
1. All voltages are referenced to ground.
2. Measured with outputs open.
3. V
CC
= 5V @25°C. Delays accurate on rising edges within
±2
ns.
4. See Test Conditions below.
5. All output delays in the same speed output tend to vary unidirectionally with temperature or voltage
range (i.e., if Out 2 slows down, all other outputs also slow down).
6. Period specifications may be exceeded; however, accuracy will be application-sensitive (decoupling,
layout, etc.).
7. t
PU
= 0 ms for Out 1 through Out 4.
TERMINOLOGY
Period:
The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
t
WI
(Pulse Width):
The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
t
RISE
(Input Rise Time):
The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
t
FALL
(Input Fall Time):
The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
t
PLH
(Time Delay, Rising):
The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of the corresponding output pulse.
TEST SETUP DESCRIPTION
Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1007.
The input waveform is produced by a precision pulse generator under software control. Time delays are
measured by a time interval counter (20 ps resolution) connected between the input and each output. Each
output is selected and connected to the counter by a VHF switch control unit. All measurements are fully
automated, with each instrument controlled by a central computer over an IEEE 488 bus.
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单片机
