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DS1012M-D20

Silicon Delay Line, 2-Func, 1-Tap, True Output, CMOS, PDIP8, 0.300 INCH, DIP-8

器件类别:逻辑    逻辑   

厂商名称:DALLAS

厂商官网:http://www.dalsemi.com

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器件参数
参数名称
属性值
是否Rohs认证
不符合
包装说明
0.300 INCH, DIP-8
Reach Compliance Code
unknown
其他特性
OUT3 = D3 NAND D4, OUT4 = D3 XOR D4
系列
1000
输入频率最大值(fmax)
10.101 MHz
JESD-30 代码
R-PDIP-T8
JESD-609代码
e0
逻辑集成电路类型
SILICON DELAY LINE
功能数量
2
抽头/阶步数
1
端子数量
8
最高工作温度
70 °C
最低工作温度
输出极性
TRUE
封装主体材料
PLASTIC/EPOXY
封装代码
DIP
封装等效代码
DIP8,.3
封装形状
RECTANGULAR
封装形式
IN-LINE
峰值回流温度(摄氏度)
NOT SPECIFIED
电源
5 V
最大电源电流(ICC)
70 mA
可编程延迟线
NO
Prop。Delay @ Nom-Sup
16.5 ns
认证状态
Not Qualified
最大供电电压 (Vsup)
5.25 V
最小供电电压 (Vsup)
4.75 V
标称供电电压 (Vsup)
5 V
表面贴装
NO
技术
CMOS
温度等级
COMMERCIAL
端子面层
Tin/Lead (Sn/Pb)
端子形式
THROUGH-HOLE
端子节距
2.54 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
NOT SPECIFIED
总延迟标称(td)
16.5 ns
Base Number Matches
1
文档预览
DS1012
DS1012
2-in-1 Sub-Miniature Silicon
Delay Line with Logic
FEATURES
PIN ASSIGNMENT
IN1
OUT3
OUT1
GND
1
2
3
4
8
7
6
5
V
CC
IN2
OUT2
OUT4
All-silicon time delay
53
µW
max. CMOS quiescent mode
Surface mount 8-pin mini-SOIC and standard 8-pin
DIP
2 independent buffered delays per input
Option of complemented output(s)
Option of timed AND, NAND, OR, NOR, XOR, XNOR,
HALF-XOR and HALF-XNOR logic outputs
DS1012M 8-PIN DIP (300 MIL)
See Mech. Drawings
Section
IN1
OUT3
OUT1
GND
1
2
3
4
8
7
6
5
V
CC
IN2
OUT2
OUT4
Delay tolerance:
±1.5
ns (delays: 3-10 ns),
±2.0
ns (delays: 11-40 ns)
Vapor phase, IR and wave solderability
Economical
TTL/CMOS-compatible
Quick turn prototypes
Custom delays and logic options available
DS1012Z 8-PIN SOIC (150 MIL)
See Mech. Drawings
Section
PIN DESCRIPTION
IN1, IN2
OUT1, OUT2
OUT3, OUT4
GND
V
CC
Inputs
Outputs (delays)
Outputs (delays, logic)
Ground
+5 Volts
DESCRIPTION
In its most simple configuration, the DS1012 2-in-1
Sub-Miniature Silicon Delay Line Chip provides two in-
puts, each of which in turn provides independent delays
to a pair of outputs. The DS1012-1 and DS1012-3 are
examples of catalog parts having this basic configura-
tion. Any of the four outputs can be inverted at the time
of manufacture.
For applications requiring two-input timed logic func-
tions, at the time of manufacture the simple delay on
OUT4 can be replaced by one of the following: OR,
NOR, XOR, or XNOR. Similarly, a timed AND, NAND,
HALF-XOR (D3 AND D4), or NOT HALF-XOR (D3 OR
D4) can be substituted for the simple delay on OUT3.
DS1012-2, DS1012-4, and DS1012-5 are examples of
catalog parts configured with logic functions on OUT3
and OUT4. Note that DS1012-2 also utilizes an output
inversion on OUT2.
In any configuration, delays D1 (t
D1
) and D2 (t
D2
) can be
specified within the range of ~3 ns to 10 ns. Delays D3
(t
D3
) and D4 (t
D4
) can be specified to have values be-
tween ~3 ns and 40 ns. The worst case leading edge
delay accuracy at nominal voltage and room tempera-
ture is
±2
ns. The DS1012 is offered in two packages: an
8-pin DIP and an 8-pin 150 mil wide mini-SOIC.
Dallas Semiconductor offers the DS1012 in a wide vari-
ety of custom delay and logic configurations. For special
requests and quick turn delivery, call (972) 371–4348.
021798 1/7
DS1012
LOGIC DIAGRAM
Figure 1
IN1
DELAY
D1
OUT1
DELAY
D3
FUNCTION
f3
OUT3
DELAY
D4
FUNCTION
f4
OUT4
IN2
DELAY
D2
OUT2
Function f3 can be one of the following:
D3
D3 AND D4
D3 HALF-XOR D4
Function f4 can be one of the following:
D4
D3 OR D4
D3 XOR D4
NOTE:
D4
D3 NOR D4
D3 XNOR D4
D3
D3 NAND D4
D3 HALF-XNOR D4
Any output(s) can be inverted at time of manufacture.
If D1 > 10 ns, D1 = D3.
If D2 > 10 ns, D2 = D4.
021798 2/7
DS1012
PART NUMBER DELAY AND CONFIGURATION
Table 1
CATALOG
P/N
DS1012-1
DS1012-2
DS1012-3
DS1012-4
DS1012-5
DS1012-7
DS1012–9
DS1012-D16
DS1012-D20
DS1012-D25
DS1012-D33
DS1012-D50
DS1012-V20
DS1012-V40
DS1012-V50
DS1012-V60
NOTE:
t
D1
(ns)
5
5
3
5
10
15
5
4
4
4
4
4
25
12.5
10
8.3
t
D2
(ns)
5
5
7
5
10
4
25
19.6
16.5
14
11.5
9
50
25
20
8.3
t
D3
(ns)
10
10
10
25
5
4
5
4
4
4
4
4
25
12.5
10
8.3
t
D4
(ns)
10
10
40
25
5
14
25
19.6
16.5
14
11.5
9
50
25
20
8.3
OUT1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
OUT2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
OUT3
D3
D3.D4
D3
D3HXD4
D3.D4
D3
D3HXD4
D3.D4
D3.D4
D3.D4
D3.D4
D3.D4
D3.D4
D3.D4
D3.D4
D3.D4
OUT4
D4
D3+D4
D4
D3XD4
D3+D4
D3XD4
D3XD4
D3XD4
D3XD4
D3XD4
D3XD4
D3XD4
D3+D4
D3XD4
D3XD4
D3+D4
. = AND, + = OR, X = XOR, HX = HALF–XOR
Contact Dallas Semiconductor for information on custom configurations and timing delays.
TEST CIRCUIT
Figure 2
+5V
Z
0
= 50
START TIP
(TIME INTERVAL
PROBE)
PULSE
GENERATOR
+5V
STOP
TIP
DEVICE
UNDER
TEST
VHF
SWITCH
CONTROL
UNIT
Z
0
= 50
TIME
INTERVAL
COUNTER
74F04
VHF SWITCH
CONTROL UNIT
021798 3/7
DS1012
TEST SETUP DESCRIPTION
Figure 2 illustrates the hardware configuration used for
measuring the timing parameters on the DS1012. The
input waveform is produced by a precision pulse gener-
ator under software control connected to the inputs by
VHF switch control units. Time delays are measured by
a time interval counter (20 ps resolution) connected be-
tween the inputs and the outputs. Outputs are con-
nected to the counter by a VHF switch control unit. All
measurements are fully automated, with each instru-
ment controlled by a central computer over an IEEE 488
bus.
TEST CONDITIONS
INPUT:
Ambient Temperature:
Supply Voltage (V
CC
):
Input Pulse:
Source Impedance:
Rise and Fall Time:
Pulse Width:
Period:
25°C
±
3°C
5.0V
±
0.1V
High = 3.0V
±
0.1V
Low = 0.0V
±
0.1V
50 ohms max.
3.0 ns max.
50 ns
100 ns
OUTPUT:
Each output is loaded with a 74F04. Delay is measured
between the 1.5V level of the rising edge of the input sig-
nal and the 1.5V level of the corresponding edge of the
output.
NOTE:
These conditions are for test only and do
not restrict the operation of the device un-
der other data sheet conditions.
021798 4/7
DS1012
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
-1.0V to +7.0V
0°C to 70°C
-55°C to +125°C
260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS
PARAMETER
Supply Voltage
High Level Input Voltage
Low Level Input Voltage
Input Leakage Current
Active Current
Quiescent Current
High Level Output Current
Low Level Output Current
SYMBOL
V
CC
V
IH
V
IL
I
I
I
CC1
I
CC2
I
OH
I
OL
0.0V < V
I
< V
CC
V
CC
= MAX;
PERIOD = MIN
V
CC
= MAX.
V
CC
= MIN
V
OH
= 2.4V
V
CC
= MIN.
V
OL
= 0.5V
8.0
TEST
MIN
4.75
2.2
-0.5
-1.0
(0°C to 70°C; V
CC
= 5.0V
±
5%)
TYP
5.00
MAX
5.25
V
CC
+0.5
0.8
1.0
40.0
70.0
10
-1.0
UNITS
V
V
V
µA
mA
µA
mA
mA
2
5
NOTES
1
1
1
AC ELECTRICAL CHARACTERISTICS
PARAMETER
Input Pulse Width
Input to Output (leading edge)
Power-up Time
SYMBOL
t
WI
t
D1
, t
D2
,
t
D3
, t
D4
t
PU
Period
2(t
WI
)
MIN
TYP
(T
A
= 25
°
C; V
CC
= 5V
±
5%)
MAX
UNITS
ns
ns
0
ns
ns
NOTES
6
3, 4
7
CAPACITANCE
PARAMETER
Input Capacitance
SYMBOL
C
IN
MIN
TYP
5
MAX
10
UNITS
pF
(T
A
= 25
°
C)
NOTES
021798 5/7
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