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DS1077
EconOscillator/Divider
www.maxim-ic.com
FEATURES
§
§
§
§
§
§
§
§
§
§
§
§
Processor-controlled or standalone solid-
state oscillator
Frequency changes on-the-fly
Dual low-jitter, synchronous fixed
frequency outputs
2-wire serial interface
Frequency outputs 8.1kHz to 133MHz
±0.5% variation over temp (+25°C to
+70°C)
±0.5% initial tolerance
Nonvolatile (NV) frequency settings
Single 5V supply
No external components
Power-down mode
Synchronous output gating
PIN ASSIGNMENT
OUT1
OUT0
V
DD
V
CC
GND
1
2
3
4
8
7
6
5
SCL
SDA
CTRL1
CTRL0
150mil SO
118mil µSOP Package
PIN DESCRIPTION
OUT1
OUT0
V
CC
GND
CTRL1
CTRL0
SDA
SCL
STANDARD FREQUENCY OPTION
Note: x denotes package option
DS1077x-133 133.333MHz to
DS1077x-125 125.000MHz to
DS1077x-120 120.000MHz to
DS1077x-100 100.000MHz to
DS1077x-66
66.666MHz to
16.2kHz
15.2kHz
14.6kHz
12.2kHz
8.1kHz
- Main Oscillator Output
- Reference Output
- Power Supply Voltage
- Ground
- Control Pin for OUT1
- Control Pin for OUT0
- 2-Wire Serial Data
Input/Output
- 2-Wire Serial Clock
ORDERING INFORMATION
Note: XXX denotes frequency option
DS1077Z-XXX
8-Pin 150mil SO
DS1077U-XXX
8-Pin 118mil µSOP
DESCRIPTION
The DS1077 is a dual-output, programmable, fixed-frequency oscillator requiring no external
components for operation. The DS1077 can be used as a processor-controlled frequency synthesizer or
as a standalone oscillator. The two synchronous output operating frequencies are user-adjustable in
submultiples of the master frequency through the use of two on-chip programmable prescalers and a
divider. The specific output frequencies chosen are stored in NV (EEPROM) memory. The DS1077
defaults to these values upon power-up.
The DS1077 features a 2-wire serial interface that allows in-circuit on-the-fly programming of the
programmable prescalers (P0 & P1) and divider (N) with the desired values being stored in NV
(EEPROM) memory. Design changes can be accommodated in-circuit on-the-fly by simply
programming different values into the device (or reprogramming previously programmed devices).
Alternatively, for fixed frequency applications, previously programmed devices can be used and no
connection to the serial interface is required. Pre-programmed devices can be ordered in customer-
requested frequencies.
The DS1077 is available in 8-pin SO or µSOP packages, allowing the generation of a clock signal
easily, economically, and using minimal board area. Chip-scale packaging is also available on request.
EconOscillator is a trademark of Dallas Semiconductor.
1 of 21
011006
DS1077
BLOCK DIAGRAM 1077
Figure1
SEL0
EN0
PDN0
Select
DIV1
0M1
0M0
1M1
1M0
EN0
SEL0
PDN0
PDN1
CONTROL
REGISTERS
P1
PRESCALER
(M DIVIDER)
PROGRAMMABLE
“N” DIVIDER
OUT1
0M1
0M0
DIV1
P0
PRESCALER
(M DIVIDER)
MUX
OUT0
MCLK
Power-Down
CONTROL
LOGIC
(TABLE 1)
Enable
INTERNAL
OSCILLATOR
CTRL0
2-WIRE
INTERFACE
1M1
1M0
Power-Down
Enable
CONTROL
LOGIC
(TABLE 2)
PDN1
SDA
SCL
2 of 21
CTRL1
DS1077
OVERVIEW
A block diagram of the DS1077 is shown in Figure 1. The DS1077 consists of four major components:
1) Internal Master Oscillator, 2) Prescalers, 3) Programmable Divider, and 4) Control Registers.
The internal oscillator is factory-trimmed to provide a master frequency (Master CLK) that can be routed
directly to the outputs (OUT0 & OUT1) or through separate prescalers (P0 & P1). OUT1 can also be
routed through an additional divider (N).
The Prescaler (P0) divides the Master Clock by 1, 2, 4, or 8 to be routed directly to the OUT0 pin.
The Prescaler (P1) divides the Master Clock by 1, 2, 4, or 8, which can be routed directly to the OUT1 pin
or to the Divider (N) input, which is then routed to the OUT1 pin.
The Programmable Divider (N) divides the Prescaler Output (P1) by any number selected between 2 and
1025 to provide the Main Output (OUT1) or it can be bypassed altogether by use of the DIV1 register bit.
The value of N is stored in the DIV register.
The Control Registers are user-programmable through a 2-wire serial interface to determine operating
frequency (values of P0, P1, & N) and modes of operation. The register values are stored in EEPROM
and therefore only need to be programmed to alter frequencies and operating modes.
PIN DESCRIPTIONS
Output 1 (OUT1)—This
pin is the main oscillator output; its frequency is determined by the control
register settings for the prescaler P1 (mode bits 1M1 & 1M0) and divider N (DIV word).
Output 0 (OUT0)—A
reference output, OUT0, is taken from the output of the reference select Mux. Its
frequency is determined by the control register settings for CTRL0 and values of Prescaler P0 (mode bits
0M1 & 0M0) (see Table 1).
Control Pin 0 (CTRL0)—A
multifunctional input pin that can be selected as a MUX SELECT,
OUTPUT ENABLE and/or a POWER-DOWN. Its function is determined by the user-programmable
control register values EN0, SEL0, and PDN0 (see Table 1).
Control Pin 1 (CTRL1)—A
multifunctional input pin that can be selected as a OUTPUT ENABLE
and/or a POWER-DOWN. Its function is determined by the user-programmable control register value of
PDN1 (see Table 2).
Serial Data Input/Output (SDA)—Input/Output
pin for the 2-wire serial interface used for data transfer.
Serial Clock Input (SCL)—Input
pin for the 2-wire serial interface used to synchronize data movement
on the serial interface.
3 of 21
DS1077
DEVICE MODE USING OUT0
Table 1
EN0
(BIT)
0
0
SEL0
(BIT)
0
1
PDN0
(BIT)
0
0
CTRL0
(PIN)
1
0
OUT0
(PIN)
HI-Z
HI-Z
CTRL0
FUNCTION
POWER-
DOWN*
DEVICE
MODE
POWER-DOWN
ACTIVE
1
MCLK/M
MUX SELECT
ACTIVE
0
MCLK
1
HI-Z
OUTPUT
1
0
0
ACTIVE
ENABLE
0
MCLK
1
HI-Z
OUTPUT
1
1
0
ACTIVE**
ENABLE
0
MCLK/M
1
HI-Z
POWER-DOWN
POWER-
X
0
1
DOWN
0
MCLK
ACTIVE
1
HI-Z
POWER-DOWN
POWER-
X
1
1
DOWN
0
MCLK/M
ACTIVE
*This mode is for applications where OUT0 is not used, but CTRL0 is used as a device shutdown.
**Default Condition
DEVICE MODE USING OUT1
Table 2
PDN1
(BIT)
0
0
1
1
CTRL1
(PIN)
0
1
0
1
CTRL1
FUNCTION
OUTPUT ENABLE
OUTPUT ENABLE
POWER-DOWN
POWER-DOWN
OUT1
OUT CLK
HI-Z
OUT CLK
HI-Z
DEVICE MODE
ACTIVE**
ACTIVE**
ACTIVE
POWER-DOWN
**Default Condition
NOTE:
Both CTRL0 and CTRL1 can be configured as power-downs. They are internally “OR” connected so that
either of the control pins can be used to provide a power-down function for the whole device, subject to
appropriate settings of the PDN0 and PDN1 register bits (see Table 3).
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