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DS1602
Elapsed Time Counter
PIN ASSIGNMENT
RST
DQ
CLK
GND
1
2
3
4
8
7
6
5
V
CC
X1
X2
V
BAT
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FEATURES
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Two 32-bit counters keep track of real-time
and elapsed time
Counters keep track of seconds for over 125
years
Battery powered counter counts seconds from
the time battery is attached until V
BAT
is less
than 2.5V
V
CC
powered counter counts seconds while
V
CC
is above V
TP
and retains the count in the
absence of V
CC
under battery backup power
Clear function resets selected counter to 0
Read/write serial port affords low pin count
Maximum current drain of less than 1 µA
from V
BAT
pin when serial port is disabled
One byte protocol defines read/write, counter
address and software clear function
8-pin DIP or optional 8-pin SOIC
Operating temperature range of -40°C to
+85°C
Reduced performance operation down to
V
CC
= 2.5V
Underwriters Laboratory (UL) recognized
DS1602
8-Pin DIP (300mil)
RST
DQ
CLK
GND
1
2
3
4
8
7
6
5
V
CC
X1
X2
V
BAT
DS1602
8-Pin SOIC (208mil)
Package Dimension Information
www.maxim-ic.com/TechSupport/DallasPackInfo.htm
PIN DESCRIPTION
RST
CLK
DQ
GND
X1, X2
V
BAT
V
CC
- Reset
- Clock
- Data Input/Output
- Ground
- Crystal Inputs
- + Battery Input
- +5V
DESCRIPTION
The DS1602 is a real-time clock/elapsed time counter designed to count seconds when V power is
CC
applied and continually count seconds under battery backup power with an additional counter regardless
of the condition of V
CC
. The continuous counter can be used to derive time of day, week, month, and year
by using a software algorithm. The V powered counter will automatically record the amount of time
CC
that V power is applied. This function is particularly useful in determining the operational time of
CC
equipment in which the DS1602 is used. Alternatively, this counter can also be used under software
control to record real-time eve nts. Communication to and from the DS1602 takes place via a 3-wire serial
port. A 1-byte protocol selects read/ write functions, counter clear functions and oscillator trim. A low
cost 32.768kHz crystal attaches directly to the X1 and X2 pins. If battery powered-only operation is
desired, the V
BAT
pin must be grounded and the V
CC
pin must be connected to the battery.
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
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093002
DS1602
OPERATION
The main elements of the DS1602 are shown in Figure 1. As shown, communications to and from the
elapsed time counter occur over a 3-wire serial port. The port is activated by driving
RST
to a high state.
With
RST
at high level, 8 bits are loaded into the protocol shift register providing read/write, register
select, register clear, and oscillator trim information. Each bit is serially input on the rising edge of the
clock input. After the first eight clock cycles have loaded the protocol register with a valid protocol,
additional clocks will output data for a read or input data for a write. V
CC
must be present to access the
DS1602. If V < V
TP
, the DS1602 goes into a battery backup mode which disables the serial port to
CC
conserve battery capacity. For battery only operations, the V
BAT
pin must be grounded and the V
CC
pin
must be connected to the battery. This will keep the DS1602 out of battery backup mode. Battery
powered operation down to 2.5V is possible with reduced speed performance on the serial port. The 32-
bit continuous counter always runs provided that a valid supply is present and the oscillator is enabled.
The 32-bit V
CC
active counter is gated by V
CC
and the internal 1Hz signal.
PROTOCOL REGISTER
The protocol bit definition is shown in Figure 2. Valid protocols and the resulting actions are shown in
Table 1. Each data transfer to the protocol register designates what action is to occur. As defined, the
MSB (bit 7 which is designated ACC) selects the 32-bit continuous counter for access. If ACC is a logical
1 the continuous counter is selected and the 32 clock cycles that follow the protocol will either read or
write this counter. If the counter is being read, the contents will be latched into a different register at the
end of protocol and the latched contents will be read out on the next 32 clock cycles. This avoids reading
garbled data if the counter is clocked by the oscillator during a read. Similarly, if the counter is to be
written, the data is buffered in a register and all 32 bits are jammed into the counter simultaneously on the
rising edge of the 32
nd
clock. The next bit (bit 6 which is designated AVC) selects the 32-bit V
CC
active
counter for access. If AVC is a logical 1 this counter is selected and the 32 clock cycles that follow will
either read or write this counter. If both bit 7 and bit 6 are written to a logic high, all clock cycles beyond
the protocol are ignored and bits 5, 4, and 3 are loaded into the oscillator trim register. A value of binary 3
(011) will give a clock accuracy of ±120 seconds per month at +25°C. Increasing the binary number
towards 7 will cause the real- time clock to run faster. Conversely, lowering the binary number towards 0
will cause the clock to run slower. Binary 000 will stop the oscillator completely. This feature can be used
to conserve battery life during storage. In this mode the I
BAT
current is reduced to 100nA maximum. In
applications where oscillator trimming is not practical or not needed, a default setting of 011 is
recommended. Bit 2 of protocol (designated CCC) is used to clear the continuous counter. When set to
logic 1, the continuous counter will reset to 0 when
RST
is taken low. Bit 1 of protocol (designated CVC)
is used to clear the V
CC
active counter. When set to logical 1, the V
CC
active counter will reset to 0 when
RST
is taken low. Both counters can be reset simultaneously by setting CCC and CVC both to a logical
1. Bit 0 of the protocol (designated RD) determines whether the 32 clocks to follow will write a counter
or read a counter. When RD is set to a logical 0 a write action will follow when RD is set to a logical 1 a
read action will follow. When sending the protocol, 8 bits should always be sent. Sending less than 8 bits
can produce erroneous results. If clearing the counters or trimming the oscillator, the data transfer can be
terminated after the 8-bit protocol is sent. However, when reading or writing the counters, 32 clock cycles
should always follow the protocol.
RESET AND CLOCK CONTROL
All data transfers are initiated by driving the
RST
input high. The
RST
input has two functions. First,
RST
turns on the serial port logic, which allows access to the protocol register for the protocol data entry.
Second, the
RST
signal provides a method of terminating the protocol transfer or the 32-bit counter
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DS1602
transfer. A clock cycle is a sequence of a rising edge followed by a falling edge. For write inputs, data
must be valid during the rising edge of the clock. Data bits are output on the falling edge of the clock
when data is being read. All data transfers terminate if the
RST
input is transitioned low and the DQ pin
goes to a high- impedance state.
RST
should only be transitioned low while the clock is high to avoid
disturbing the last bit of data. All data transfers must consist of 8 bits when transferring protocol only or
8 + 32 bits when reading or writing either counter. Data transfer is illustrated in Figure 3.
DATA INPUT
Following the 8-bit protocol that inputs write mode, 32 bits of data are written to the selected counter on
the rising edge of the next 32 CLK cycles. After 32 bits have been entered any additional CLK cycles will
be ignored until
RST
is transitioned low to end data transfer, and then high again to begin new data
transfer.
DATA OUTPUT
Following the eight CLK cycles that input read mode protocol, 32 bits of data will be output from the
selected counter on the next 32 CLK cycles. The first data bit to be transmitted from the selected 32-bit
counter occurs on the falling edge after the last bit of protocol is written. When transmitting data from the
selected 32-bit counter,
RST
must remain at high level as a transition to low level will terminate data
transfer. Data is driven out the DQ pin as long as CLK is low. When CLK is high the DQ pin is tristated.
CRYSTAL SELECTION
A standard 32.768kHz quartz crystal can be directly connected to the DS1602 via pins 1 and 2 (X1, X2).
The crystal selected for use should have a specified load capacitance (C
L
) of 6pF. For more information
on crystal selection and crystal layout considerations, please consult
Application Note 58: Crystal
Considerations with Dallas Real-Time Clocks.
BATTERY SELECTION
The battery selected for use with the DS1602 should have an output voltage between 2.5V and 3.5V. A
lithium battery of 35mAh or greater will run the elapsed time counter for over 10 years in the absence of
power. Small lithium coin cell batteries produce both the proper output voltage and have the capacity to
supply the DS1602 for the useable lifetime of the equipment where they are installed.
PIN DESCRIPTIONS
Vcc, GND –
DC power is provided to the device on these pins. V
CC
is the +5V input. When 5V is applied
within normal limits, the device is fully accessible and data can be written and read. When a 3V battery is
connected to the device and V
CC
is below 1.25 x V
BAT
, reads and writes are inhibited. As V
CC
falls below
V
BAT
the continuous counter is switched over to the external power supply (nominal 3.0V DC) at V
BAT
.
CLK (Serial Clock Input) –
CLK is used to synchronize data movement on the serial interface.
DQ (Data Input/Output) –
The DQ pin is the bidirectional data pin for the 3-wire interface.
RST (Reset) –
The reset signal must be asserted high during a read or a write.
X1, X2 –
Connections for a standard 32.768kHz quartz crystal. The internal oscillator is designed for
operation with a crystal having a specified load capacitance of 6pF. For more information on crystal
selection and crystal layout considerations, refer to
Application Note 58: Crystal Considerations with
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DS1602
Dallas Real-Time Clocks.
The DS1602 can also be driven by an external 32.768kHz oscillator. In this
configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated.
V
BAT
–
Battery input for any standard 3V lithium cell or other energy source. Battery voltage must be
held between 2.5V and 3.5V for proper operation. The nominal write-protect trip-point voltage at which
access to the DS1602 is denied is set by the internal circuitry as 1.25 x V
BAT
nominal. UL recognized to
ensure against reverse charging current when used in conjunction with a lithium battery. See “Conditions
of Acceptability” at
www.maxim- ic.com/TechSupport/QA/ntrl.htm.
Figure 1. ELAPSED TIME COUNTER BLOCK DIAGRAM
Figure 2. PROTOCOL BIT MAP
7
ACC
6
AVC
5
OSC2
4
OSC1
3
OSC0
2
CCC
1
CVC
0
RD
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DS1602
Table 1. VALID PROTOCOLS
ACTION
ACC
AVC
OSC2
PROTOCOL
OSC1
OSC0
CCC
CVC
RD
FUNCTION
Read
Continuous
Counter
1
0
X
X
X
X
X
1
Write
Continuous
Counter
1
0
X
X
X
X
X
0
Read V
CC
Active
Counter
0
1
X
X
X
X
X
1
Write V
CC
Active
Counter
0
1
X
X
X
X
X
0
Clear
Continuous
Counter
0
0
X
X
X
1
X
X
Clear V
CC
Active
Counter
0
0
X
X
X
X
1
X
Set Oscillator
Trim Bits
X = Don’t Care
1
1
A
B
C
X
X
0
Output continuous
counter on the 32 clocks
following protocol.
Oscillator trim register
is not updated. Counters
are not reset.
Input data to continuous
counter on the 32 clocks
following protocol.
Oscillator trim register
is not updated. Counters
are not reset.
Output V
CC
active
counter on the 32 clocks
following protocol,
oscillator trim register
is not updated. Counters
are not reset.
Input data to continuous
counter on the 32 clocks
following protocol.
Oscillator trim register
is not updated. Counters
are not reset.
Resets the continuous
counter to all zeros at
the end of protocol.
Oscillator trim register
is not updated.
Resets the V
CC
active
counter to all zeros at
the end of protocol.
Oscillator trim register
is not updated.
Sets the oscillator trim
register to a value of
ABC. Counters are
unaffected.
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