19-5212; Rev 4/10
DS1705/DS1706
3.3V and 5.0V MicroMonitor
www.maxim-ic.com
FEATURES
Halts and restarts an out-of-control
microprocessor
Holds microprocessor in check during power
transients
Automatically restarts microprocessor after
power failure
Monitors pushbutton for external override
Accurate 5%, 10% or 20% resets for 3.3V
systems and 5% or 10% resets for 5.0V
systems
Eliminates the need for discrete components
3.3V 20% tolerance for use with 3.0V
systems
Pin-compatible with the MAXIM
MAX705/MAX706 in 8-pin DIP, 8-pin SOIC,
and
-SOP
8-pin DIP, 8-pin SOIC and 8-pin
-SOP
packages
Industrial temperature range -40C to +85C
PIN ASSIGNMENT
PBRST
V
CC
GND
IN
1
2
3
4
8
7
6
5
WDS
RST
ST
NMI
8-Pin DIP (300 -mil)
PBRST
V
CC
GND
IN
1
2
3
4
8
7
6
5
WDS
RST(*RST)
ST
NMI
8-Pin SOIC (150-mil)
RST(*RST)
WDS
PBRST
V
CC
1
2
3
4
8
7
6
5
ST
NMI
IN
GND
8-Pin
-SOP
(118-mil)
See Mech. Drawings Section on website
DS1705 and DS1706_R/S/T
(*DS1706L and DS1706P)
PIN DESCRIPTION
PBRST
V
CC
GND
IN
NMI
ST
RST
*RST
WDS
- Pushbutton Reset Input
- Power Supply
- Ground
- Input
- Non-maskable Interrupt
- Strobe Input
- Active Low Reset Output
- Active High Reset Output
(DS1706P and DS1706L only)
- Watchdog Status Output
DESCRIPTION
The DS1705/DS1706 3.3- or 5.0-Volt MicroMonitor monitors three vital conditions for a microprocessor:
power supply, software execution, and external override. A precision temperature compensated reference
and comparator circuit monitor the status of V
CC
at the device and at an upstream point for maximum
protection. When the sense input detects an out-of-tolerance condition, a non-maskable interrupt is
generated. As the voltage at the device degrades, an internal power fail signal is generated which forces
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DS1705/DS1706
the reset to an active state. When V
CC
returns to an in-tolerance condition, the reset signal is kept in the
active state for a minimum of 130 ms to allow the power supply and processor to stabilize.
The second function the DS1705/DS1706 performs is pushbutton reset control. The DS1705/DS1706
debounces the pushbutton input and guarantees an active reset pulse width of 130 ms minimum.
The third function is a watchdog timer. The DS1705/DS1706 has an internal timer that forces the
WDS
output signal to the active state if the strobe input is not driven low prior to time-out.
OPERATION
Power Monitor
The DS1705/DS1706 detects out-of-tolerance power supply conditions and warns a processor-based
system of impending power failure. When V
CC
falls below the minimum V
CC
tolerance, a comparator
outputs the
RST
(or RST) signal.
RST
(or RST) is an excellent control signal for a microprocessor, as
processing is stopped at the last possible moment of valid V
CC
. On power-up,
RST
(or RST) are kept
active for a minimum of 130 ms to allow the power supply and processor to stabilize.
Pushbutton Reset
The DS1705/DS1706 provides an input pin for direct connection to a pushbutton reset (see Figure 2). The
pushbutton reset input requires an active low signal. Internally, this input is debounced and timed such
that a
RST
(or RST) signal of at least 130 ms minimum will be generated. The 130 ms delay commences
as the pushbutton reset input is released from the low level. The pushbutton can be initiated by connecting
the
WDS
or
NMI
outputs to the
PBRST
input as shown in Figure 3.
Non-Maskable Interrupt
The DS1705/DS1706 generates a non-maskable interrupt (
NMI
) for early warning of a power failure. A
precision comparator monitors the voltage level at the IN pin relative to an on-chip reference generated
by an internal band gap. The IN pin is a high impedance input allowing for a user-defined sense point. An
external resistor voltage divider network (Figure 5) is used to interface with high voltage signals. This
sense point may be derived from a regulated supply or from a higher DC voltage level closer to the main
system power input. Since the IN trip point V
TP
is 1.25 volts, the proper values for R1 and R2 can be
determined by the equation as shown in Figure 5. Proper operation of the DS1705/DS1706 requires that
the voltage at the IN pin be limited to V
CC
. Therefore, the maximum allowable voltage at the supply being
monitored (V
MAX
) can also be derived as shown in Figure 5. A simple approach to solving the equation is
to select a value for R2 high enough to keep power consumption low, and solve for R1. The flexibility of
the IN input pin allows for detection of power loss at the earliest point in a power supply system,
maximizing the amount of time for system shutdown between
NMI
and
RST
(or RST).
When the supply being monitored decays to the voltage sense point, the DS1705/DS1706 pulses the
NMI
output to the active state for a minimum 200
s.
The
NMI
power-fail detection circuitry also has built-in
hysteresis of 100
V.
The supply must be below the voltage sense point for approximately 5
s
before a
low
NMI
will be generated. In this way, power supply noise is removed from the monitoring function,
preventing false interrupts. During a power-up, any detected IN pin levels below V
TP
by the comparator
are disabled from generating an interrupt until V
CC
rises to V
CCTP
. As a result, any potential
NMI
pulse
will not be initiated until V
CC
reaches V
CCTP
.
Connecting
NMI
to
PBRST
would allow non-maskable interrupt to generate an automatic reset when an
out-of-tolerance condition occurred in a monitored supply. An example is shown in Figure 3.
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DS1705/DS1706
Watchdog Timer
The watchdog timer function forces
WDS
signals active when the
ST
input is not clocked within the 1
second time-out period. Time-out of the watchdog starts when
RST
(or RST) becomes inactive. If a high-
to-low transition occurs on the
ST
input pin prior to time-out, the watchdog timer is reset and begins to
time out again. If the watchdog timer is allowed to time out, the
WDS
signal is driven active (low) for a
minimum of 130 ms. The
ST
input can be derived from many microprocessor outputs. The typical signals
used are the microprocessors address signals, data signals, or control signals. When the microprocessor
functions normally, these signals would, as a matter of routine, cause the watchdog to be reset prior to
time-out. To guarantee that the watchdog timer does not time out, a high-to-low transition must occur at
or less than the minimum watchdog time-out of 1 second. A typical circuit example is shown in Figure 6.
MICROMONITOR BLOCK DIAGRAM
Figure 1
40k
180k
PUSH-BUTTON RESET
Figure 2
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DS1705/DS1706
PUSH-BUTTON RESET CONTROLLED BY
NMI
AND
WDS
Figure 3
TIMING DIAGRAM: PUSHBUTTON RESET
Figure 4
NON-MASKABLE INTERRUPT CIRCUIT EXAMPLE
Figure 5
V
SENSE
=
R1 R2
X 1.25
R2
V
MAX
=
V
SENSE
X V
CC
V
TP
Example:
V
SENSE
= 4.50V at the trip point
V
CC
= 3.3V
10 kΩ = R2
4.50
X 3.3 = 11.88V maximum
1.25
4.5 =
R1
10k
X 1.25
10k
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Therefore:
R1 = 26 kΩ
DS1705/DS1706
WATCHDOG TIMER
Figure 6
TIMING DIAGRAM: STROBE INPUT
Figure 7
TIMING DIAGRAM: NON-MASKABLE INTERRUPT
Figure 8
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