DS1747/DS1747P
Y2K-Compliant, Nonvolatile Timekeeping RAMs
www.maxim-ic.com
FEATURES
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Integrated NV SRAM, Real-Time Clock
(RTC), Crystal, Power-Fail Control Circuit,
and Lithium Energy Source
Clock Registers are Accessed Identically to
the Static RAM. These Registers are Resident
in the Eight Top RAM Locations.
Century Byte Register (Y2K Compliant)
Totally Nonvolatile with Over 10 Years of
Operation in the Absence of Power
BCD-Coded Century, Year, Month, Date,
Day, Hours, Minutes, and Seconds with
Automatic Leap-Year Compensation Valid
Up to the Year 2100
Battery Voltage-Level Indicator Flag
Power-Fail Write Protection Allows for ±10%
V
CC
Power-Supply Tolerance
Lithium Energy Source is Electrically
Disconnected to Retain Freshness Until
Power is Applied for the First Time
DIP Module Only:
Standard JEDEC Byte-Wide 512k x 8 Static
RAM Pinout
PowerCap
Ò
Module Board Only:
Surface-Mountable Package for Direct
Connection to PowerCap Containing
Battery and Crystal
Replaceable Battery (PowerCap)
Power-On Reset Output
Pin-for-Pin Compatible with Other Densities
of DS174xP Timekeeping RAM
Also Available in Industrial Temperature
Range: -40°C to +85°C
PIN CONFIGURATIONS
TOP VIEW
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
32
Dallas
31
2
Semiconductor
30
3
DS1747
29
4
28
5
27
6
26
7
25
8
24
9
23
10
22
11
21
12
13
14
15
16
20
19
18
17
V
CC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
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Encapsulated DIP
(512k x 8)
N.C.
A15
A16
RST
V
CC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Dallas
Semiconductor
DS1747P
X1
GND
V
BAT
X2
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
A18
A17
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
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PowerCap Module Board
(Uses DS9034PCX PowerCap)
PowerCap is a registered trademark of Dallas Semiconductor.
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
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REV: 011204
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
PIN DESCRIPTION
A0–A18
CE
OE
WE
V
CC
GND
DQ0–DQ7
N.C.
RST
X1, X2
V
BAT
– Address Input
– Chip Enable
– Output Enable
– Write Enable
– Power-Supply Input
– Ground
– Data Input/Output
– No Connection
– Power-On Reset Output (PowerCap Module board only)
– Crystal Connection
– Battery Connection
ORDERING INFORMATION
PART
DS1747-70
DS1747-70IND
DS1747P-70
DS1747P-70IND
DS1747W-120
DS1747W-120IND
DS1747WP-120
DS1747WP-120IND
TEMP RANGE
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
PIN-PACKAGE
32 EDIP (0.740a)
32 EDIP (0.740a)
34 PowerCap
34 PowerCap
32 EDIP (0.740a)
32 EDIP (0.740a)
34 PowerCap
34 PowerCap
TOP MARK
DS1747-70
DS1747-70 IND
DS1747P-70
DS1747P-70 IND
DS1747W-120
DS1747W-120 IND
DS1747WP-120
DS1747WP-120 IND
DESCRIPTION
The DS1747 is a full-function, year-2000-compliant (Y2KC), real-time clock/calendar (RTC) and
512k x 8 nonvolatile static RAM. User access to all registers within the DS1747 is accomplished with a
byte-wide interface as shown in Figure 1. The RTC information and control bits reside in the eight
uppermost RAM locations. The RTC registers contain century, year, month, date, day, hours, minutes,
and seconds data in 24-hour BCD format. Corrections for the date of each month and leap year are made
automatically. The RTC clock registers are double buffered to avoid access of incorrect data that can
occur during clock update cycles. The double-buffered system also prevents time loss as the
timekeeping countdown continues unabated by access to time register data. The DS1747 also contains
its own power-fail circuitry that deselects the device when the V
CC
supply is in an out-of-tolerance
condition. This feature prevents loss of data from unpredictable system operation brought on by low V
CC
as errant access and update cycles are avoided.
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DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
Figure 1. Block Diagram
Dallas
Semiconductor
DS1747
PACKAGES
The DS1747 is available in two packages (32-pin DIP and 34-pin PowerCap module). The 32-pin DIP
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap Module Board is designed with contacts for connection to a separate PowerCap
(DS9034PCX) that contains the crystal and battery. This design allows the Power-Cap to be mounted on
top of the DS1747P after the completion of the surface mount process. Mounting the PowerCap after the
surface mount process prevents damage to the crystal and battery due to the high temperatures required
for solder reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board
and PowerCap are ordered separately and shipped in separate containers. The part number for the
PowerCap is DS9034PCX.
CLOCK OPERATIONS—READING THE CLOCK
While the double-buffered register structure reduces the chance of reading incorrect data, internal
updates to the DS1747 clock registers should be halted before clock data is read to prevent reading of
data in transition. However, halting the internal clock register updating process does not affect clock
accuracy. Updating is halted when a one is written into the read bit, bit 6 of the century register, see
Table 2. As long as a one remains in that position, updating is halted. After a halt is issued, the registers
reflect the count, that is day, date, and time that was current at the moment the halt command was
issued. However, the internal clock registers of the double-buffered system continue to update so that
the clock accuracy is not affected by the access of data. All the DS1747 registers are updated
simultaneously after the internal clock register updating process has been re-enabled. Updating is within
a second after the read bit is written to zero. The READ bit must be set to a zero for a minimum of
500
ms
to ensure the external registers will be updated.
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DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
Table 1. Truth Table
V
CC
V
CC
>V
PF
V
SO
<V
CC
<V
PF
V
CC
<V
SO
<V
PF
CE
V
IH
V
IL
V
IL
V
IL
X
X
OE
X
X
V
IL
V
IH
X
X
WE
X
V
IL
V
IH
V
IH
X
X
MODE
Deselect
Write
Read
Read
Deselect
Deselect
DQ
High-Z
Data In
Data Out
High-Z
High-Z
High-Z
POWER
Standby
Active
Active
Active
CMOS Standby
Data-Retention
Mode
SETTING THE CLOCK
As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a one, like the
read bit, halts updates to the DS1747 registers. The user can then load them with the correct day, date
and time data in 24 hour BCD format. Resetting the write bit to a zero then transfers those values to the
actual clock counters and allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned
off to minimize current drain from the battery. The
OSC
bit is the MSB (bit 7) of the seconds registers,
see Table 2. Setting it to a one stops the oscillator.
FREQUENCY TEST BIT
As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to
logic “1” and the oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the
seconds register is being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for
access remain valid (i.e.,
CE
low,
OE
low,
WE
high, and address for seconds register remain valid and
stable).
CLOCK ACCURACY (DIP MODULE)
The DS1747 is guaranteed to keep time accuracy to within
±1
minute per month at 25°C. The RTC is
calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements, and does not
require additional calibration. For this reason, methods of field clock calibration are not available and
not necessary. The electrical environment also affects the clock accuracy, and caution should be taken to
place the RTC in the lowest-level EMI section of the PC board layout. For additional information, please
refer to
Application Note 58.
CLOCK ACCURACY (PowerCap MODULE)
The DS1747 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module typically keeps time accuracy to within
±1.53
minutes per month (35 ppm) at 25°C. Clock
accuracy is also affected by the electrical environment and caution should be taken to place the RTC in
the lowest-level EMI section of the PC board layout. For additional information, please refer to
Application Note 58.
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DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
Table 2. Register Map
ADDRESS
7FFFF
7FFFE
7FFFD
7FFFC
7FFFB
7FFFA
7FFF9
7FFF8
OSC
= Stop Bit
W = Write Bit
DATA
B7
X
X
BF
X
X
OSC
W
B6
10 Year
X
X
FT
X
10 Month
10 Date
X
X
10 Hour
10 Minutes
10 Seconds
10 Century
R = Read Bit
X = See Note
B5
X
B4
B3
B2
Year
Month
Date
B1
B0
FUNCTION
Year
Month
Date
Day
Hour
Minutes
Seconds
Century
RANGE
00-99
01-12
01-31
01-07
00-23
00-59
00-59
00-39
X
Day
Hour
Minutes
Seconds
Century
FT = Frequency Test
BF = Battery Flag
R
NOTE:
All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1747 is in the read mode whenever
OE
(output enable) is low,
WE
(write enable) is high, and
CE
(chip enable) is low. The device architecture allows ripple-through access to any of the address locations
in the NV SRAM. Valid data will be available at the DQ pins within t
AA
after the last address input is
stable, providing that the
CE
and
OE
access times and states are satisfied. If
CE
or
OE
access times and
states are not met, valid data will be available at the latter of chip-enable access (t
CEA
)
or at output enable
access time (t
OEA
)
. The state of the data input/output pins (DQ) is controlled by
CE
and
OE.
If the
outputs are activated before t
AA
, the data lines are driven to an intermediate state until t
AA.
If the address
inputs are changed while
CE
and
OE
remain valid, output data will remain valid for output data hold
time (t
OH
) but will then go indeterminate until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1747 is in the write mode whenever
WE,
and
CE
are in their active state. The start of a write is
referenced to the latter occurring transition of
WE
or
CE.
The addresses must be held valid throughout
the cycle.
CE
or
WE
must return inactive for a minimum of t
WR
prior to the initiation of another read or
write cycle. Data in must be valid t
DS
prior to the end of write and remain valid for t
DH
afterward. In a
typical application, the
OE
signal will be high during a write cycle. However,
OE
can be active provided
that care is taken with the data bus to avoid bus contention. If
OE
is low prior to
WE
transitioning low
the data bus can become active with read data defined by the address inputs. A low transition on
WE
will then disable the output t
WEZ
after
WE
goes active.
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