DS1963L
4k-BIT MONETARY iButton™
www.dalsemi.com
SPECIAL FEATURES
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4096 bits of read/write nonvolatile memory
Overdrive mode boosts communication
speed to 142 kbits per second
256-bit scratchpad ensures integrity of data
transfer
Memory partitioned into 256-bit pages for
packetizing data
Data integrity assured with strict read/write
protocols
Four 32-bit read-only non rolling-over page
write cycle counters
32 factory-preset tamper-detect bits to
indicate physical intrusion
On-chip 16-bit CRC generator for
safeguarding data transfers
Operating temperature range from -40°C to
+70°C
Over 10 years of data retention
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Button shape is self-aligning with cup-
shaped probes
Durable stainless steel case engraved with
registration number withstands harsh
environments
Easily affixed with self-stick adhesive
backing, latched by its flange, or locked with
a ring pressed onto its rim
Presence detector acknowledges when reader
first applies voltage
Meets UL#913 (4th Edit.); Intrinsically Safe
Apparatus, approved under Entity Concept
for use in Class I, Division 1, Group A, B, C
and D Locations (application pending)
F5 MICROCAN
TM
5.89
0.36
0.51
c
1993
COMMON iButton FEATURES
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Unique, factory-lasered and tested 64-bit
registration number (8-bit family code + 48-
bit serial number + 8-bit CRC tester) assures
absolute traceability because no two parts are
alike
Multidrop controller for MicroLAN
Digital identification and information by
momentary contact
Chip-based data carrier compactly stores
information
Can be accessed while affixed to object
Economically communicates to host with a
single digital signal at 16.3 kbits per second
Standard 16-mm diameter and 1-Wire
TM
protocol ensure compatibility with iButton
device family
2B
16.25
YYWW REGISTERED RR
1A
17.35
000000FBD8B3
DATA
GROUND
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All dimensions in millimeters.
ORDERING INFORMATION
DS1963L-F5
DS9096P
DS9101
DS9093RA
DS9093F
DS9092
F5 MicroCan
Self-Stick Adhesive Pad
Multi-Purpose Clip
Mounting Lock Ring
Snap-In Fob
iButton Probe
EXAMPLES OF ACCESSORIES
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090399
DS1963L
iButton DESCRIPTION
The DS1963L Monetary iButton is a rugged read/write data carrier that acts as a localized database that
can be easily accessed with minimal hardware. The nonvolatile memory offers a simple solution to
storing and retrieving information pertaining to the object to which the iButton is associated. Data is
transferred serially via the 1-Wire protocol which requires only a single data lead and a ground return.
The scratchpad is an additional page that acts as a buffer when writing to memory. Data is first written
to the scratchpad where it can be read back. After the data has been verified, a copy scratchpad
command will transfer the data to memory. This process ensures data integrity when modifying the
memory. A 48-bit serial number is factory lasered into each DS1963L to provide a guaranteed unique
identity which allows for absolute traceability. The durable MicroCan package is highly resistant to
environmental hazards such as dirt, moisture, and shock. Its compact coin-shaped profile is self-aligning
with mating receptacles, allowing the DS1963L to be easily used by human operators. Accessories
permit the DS1963L to be mounted on almost any surface including plastic key fobs, photo-ID badges
and printed circuit boards.
APPLICATION
The DS1963L Monetary iButton can store encrypted data which represents money. The unique
registration number, the page write cycle counters, CRC generator and tamper-detect bits prevent
unauthorized refilling of the purses. Four independent change purses can be randomly accessed from
the on-chip directory. Tamper-detect bits report if the purses have experienced physical tampering. Each
write cycle (“Monetary Transaction”) generates a unique number to audit the dispensing and refilling of
the purses. A change purse can be decremented with less than 100 ms touch dwell time for rapid
processing in crowded public facilities.
OVERVIEW
The block diagram in Figure 1 shows the relationships between the major control and memory sections of
the DS1963L. The DS1963L has four main data components: 1) 64-bit lasered ROM, 2) 256-bit
scratchpad, 3) 4096-bit SRAM, and 4) four 32-bit read-only page write cycle counters. The hierarchical
structure of the 1-Wire protocol is shown in Figure 2. Each of these counters is associated with one of the
256-bit memory pages. The four counters of the DS1963L are associated with pages 12 to 15. The
contents of the counter are read together with the memory data using a special command. The bus master
must first provide one of the six ROM Function Commands, 1) Read ROM, 2) Match ROM, 3) Search
ROM, 4) Skip ROM, 5) Overdrive-Skip ROM or 6) Overdrive-Match ROM. Upon completion of an
Overdrive ROM command byte executed at standard speed, the device will enter Overdrive mode where
all subsequent communication occurs at a higher speed. The protocol required for these ROM function
commands is described in Figure 9. After a ROM function command is successfully executed, the
memory functions become accessible and the master may provide any one of the five memory function
commands. The protocol for these memory function commands is described in Figure 7. All data is read
and written least significant bit first.
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DS1963L
DS1963L BLOCK DIAGRAM
Figure 1
DATA
LID
CONTACT
64-BIT
LASERED
ROM
1-WIRE
FUNCTION
CONTROL
PARASITE-POWERED
CIRCUITRY
MEMORY
FUNCTION
CONTROL
256-BIT
SCRATCHPAD
MEMORY
4096-BIT
SRAM
3V
Lithium
(256-BIT PAGES)
PAGE
WRITE CYCLE
COUNTERS
PARASITE POWER
The block diagram (Figure 1) shows the parasite-powered circuitry. This circuitry “steals” power
whenever the I/O input is high. I/O will provide sufficient power as long as the specified timing and
voltage requirements are met. The advantages of parasite power are two-fold: 1) by parasiting off this
input, lithium is conserved and 2) if the lithium is exhausted for any reason, the ROM may still be read
normally.
64-BIT LASERED ROM
Each DS1963L contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family
code. The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. (See
Figure 3.) The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and
XOR gates as shown in Figure 4. The polynomial is X
8
+ X
5
+ X
4
+ 1. Additional information about the
Dallas 1-Wire Cyclic Redundancy Check is available in the Book of DS19xx iButton Standards.
The shift register bits are initialized to 0. Then starting with the least significant bit of the family code,
one bit at a time is shifted in. After the 8
th
bit of the family code has been entered, then the serial number
is entered. After the 48
th
bit of the serial number has been entered, the shift register contains the CRC
value. Shifting in the 8 bits of CRC should return the shift register to all 0s.
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DS1963L
HIERARCHCAL STRUCTURE FOR 1-WIRE PROTOCOL
Figure 2
BUS
MASTER
1-WIRE BUS
OTHER
DEVICES
DS1963L
COMMAND
LEVEL:
AVAILABLE
COMMANDS:
READ ROM
MATCH ROM
SEARCH ROM
SKIP ROM
OVERDRIVE SKIP ROM
OVERDRIVE MATCH ROM
DATA FIELD
AFFECTED:
64-BIT ROM
64-BIT ROM
64-BIT ROM
N/A
N/A
64-BIT ROM
1-WIRE ROM FUNCTION
COMMANDS (SEE FIGURE 9)
DS1963L SPECIFIC
MEMORY FUNCTION
COMMANDS
(SEE FIGURE 7)
WRITE SCRATCHPAD
READ SCRATCHPAD
COPY SCRATCHPAD
READ MEMORY
READ MEMORY
+ COUNTER
256-BIT SCRATCHPAD
256-BIT SCRATCHPAD
DATA MEMORY,
WRITE CYCLE COUNTER
DATA MEMORY
DATA MEMORY,
WRITE CYCLE COUNTER,
TAMPER-DETECT BITS
64-BIT LASERED ROM
Figure 3
MSB
8-BIT CRC CODE
MSB
LSB
48-BIT SERIAL NUMBER
8-BIT FAMILY CODE 1AH
LSB MSB
LSB MSB
LSB
1-WIRE CRC GENERATOR
Figure 4
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DS1963L
MEMORY
The memory map in Figure 5 shows a 32-byte page called the scratchpad and additional 32-byte pages
called memory. The DS1963L contains pages 0 through 15 which make up the 4096-bit SRAM. The
scratchpad is an additional page that acts as a buffer when writing to memory.
ADDRESS REGISTERS AND TRANSFER STATUS
Because of the serial data transfer, the DS1963L employs three address registers, called TA1, TA2 and
E/S (Figure 6). Registers TA1 and TA2 must be loaded with the target address to which the data will be
written or from which data will be sent to the master upon a Read command. Register E/S acts like a byte
counter and Transfer Status register. It is used to verify data integrity with write commands. Therefore,
the master only has read access to this register. The lower 5 bits of the E/S register indicate the address of
the last byte that has been written to the scratchpad. This address is called Ending Offset. Bit 5 of the E/S
register, called PF or “partial byte flag,” is set if the number of data bits sent by the master is not an
integer multiple of 8. Bit 6 has no function; it always reads 0. Note that the lowest 5 bits of the target
address also determine the address within the scratchpad, where intermediate storage of data will begin.
This address is called byte offset. If the target address (TA1) for a Write command is 03CH for example,
then the scratchpad will store incoming data beginning at the byte offset 1CH and will be full after only
four bytes. The corresponding ending offset in this example is 1FH. For best economy of speed and
efficiency, the target address for writing should point to the beginning of a new page; i.e., the byte offset
will be 0. Thus the full 32-byte capacity of the scratchpad is available, resulting also in the ending offset
of 1FH. However, it is possible to write one or several contiguous bytes somewhere within a page. The
ending offset together with the Partial Flag support the master checking the data integrity after a Write
command. The highest valued bit of the E/S register, called AA or Authorization Accepted, acts as a flag
to indicate that the data stored in the scratchpad has already been copied to the target memory address.
Writing data to the scratchpad clears this flag.
WRITING WITH VERIFICATION
To write data to the DS1963L, the scratchpad has to be used as intermediate storage. First the master
issues the Write Scratchpad command to specify the desired target address, followed by the data to be
written to the scratchpad. Under certain conditions (see Write Scratchpad command) the master will
receive an inverted CRC16 of the command, address and data at the end of the write scratchpad command
sequence. Knowing this CRC value, the master can compare it to the value it has calculated itself to
decide if the communication was successful and proceed to the Copy Scratchpad command. If the master
could not receive the CRC16, it has to send the Read Scratchpad command to read back the scratchpad to
verify data integrity. As preamble to the scratchpad data, the DS1963L repeats the target address TA1
and TA2 and sends the contents of the E/S register. If the PF flag is set, data did not arrive correctly in the
scratchpad. The master does not need to continue reading; it can start a new trial to write data to the
scratchpad. Similarly, a set AA flag indicates that the Write command was not recognized by the iButton.
If everything went correctly, both flags are cleared and the ending offset indicates the address of the last
byte written to the scratchpad. Now the master can continue reading and verifying every data byte. After
the master has verified the data, it has to send the Copy Scratchpad command. This command must be
followed exactly by the data of the three address registers TA1, TA2 and E/S. The master may obtain the
contents of these registers by reading the scratchpad or derive it from the target address and the amount of
data to be written. As soon as the DS1963L has received these bytes correctly, it will copy the data to the
requested location beginning at the target address.
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