DS2141A
T1 Controller
www.dalsemi.com
FEATURES
DS1/ISDN-PRI framing transceiver
Frames to D4, ESF, and SLC-96 formats
Parallel control port
Onboard, dual two-frame elastic store slip
buffers
Extracts and inserts robbed-bit signaling
Programmable output clocks
Onboard FDL support circuitry
5V supply; low-power CMOS
Available in 40-pin DIP and 44-pin PLCC
(DS2141Q)
Compatible with DS2186 Transmit Line
Interface, DS2187 Receive Line Interface,
DS2188 Jitter Attenuator, DS2290 T1
Isolation Stik, and DS2291 T1 Long Loop
Stik
PIN ASSIGNMENT
TCLK
TSER
TCHCLK
TPOS
TNEG
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
BTS
RD(DS)
CS
ALE(AS)
WR(R/W)
RLINK
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VDD
TSYNC
TLINK
TLCLK
INT1
INT2
RLOS/LOTC
TCHBLK
RCHBLK
LI CS
LI CLK
LI SDI
SYSCLK
RNEG
RPOS
RSYNC
RSER
RCHCLK
RCLK
RLCLK
40-Pin DIP (600-mil)
TNEG
TPOS
TCHCLK
TSER
TCLK
VDD
TSYNC
TLINK
TLCLK
INT1
INT2
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
BTS
RD(DS)
NC
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
5
4
3
2
1
44
43
42
41 40
39
38
37
36
35
44-PIN PLCC
34
33
32
31
30
29
28
RLOS/LOTC
TCHBLK
RCHBLK
LI_CS
LI_CLK
LI_SDI
NC
NC
SYSCLK
RNEG
RPOS
DESCRIPTION
The DS2141A is a comprehensive, software-driven T1 framer. It is meant to act as a slave or coprocessor
to a microcontroller or microprocessor. Quick access via the parallel control port allows a single micro to
handle many T1 lines. The DS2141A is very flexible and can be configured into numerous orientations
via software. The software orientation of the device allows the user to modify their design to conform to
future T1 specification changes. The controller contains a set of 62 8-bit internal registers which the user
can access. These internal registers are used to configure the device and obtain information from the T1
1 of 39
112099
NC
CS
ALE(AS)
WR(R/W)
RLINK
VSS
RLCLK
RCLK
RCHCLK
RSER
RSYNC
DS2141A
link. The device fully meets all of the latest T1 specifications including ANSI T1.403-1989, AT&T TR
62411 (12-90), and CCITT G.704 and G.706.
1.0 INTRODUCTION
The DS2141A T1 Controller has four main sections: the receive side, the transmit side, the line interface
controller, and the parallel control port. See the block diagram below. On the receive side, the device will
clock in the serial T1 stream via the RPOS and RNEG pins. The synchronizer will locate the frame and
multiframe patterns and establish their respective positions. This information will be used by the rest of
the receive side circuitry.
The DS2141A is an “off-line” framer, which means that all of the T1 serial stream that goes into the
device will come out of it unchanged. Once the T1 data has been framed to, the robbed-bit signaling data
and FDL can be extracted. The 2-frame elastic stores can either be enabled or bypassed.
The transmit side clocks in the unframed T1 stream at TSER and adds in the framing pattern, the robbed-
bit signaling, and the FDL. The line interface control port will update line interface devices that contain a
serial port. The parallel control port contains a multiplexed address and data structure which can be
connected to either a microcontroller or microprocessor.
DS2141A BLOCK DIAGRAM
2 of 39
DS2141A
DS2141A FEATURES
Parallel control port
Large error counters
Onboard dual 2-frame elastic store
FDL support circuitry
Robbed-bit signaling extraction and insertion
Programmable output clocks
Fully independent transmit and receive sections
Frame sync generation
Error-tolerant yellow and blue alarm detection
Output pin test mode
Payload loopback capability
SLC-96 support
Remote loop up/down code detection
Loss of transmit clock detection
Loss of receive clock detection
1's density violation detection
PIN DESCRIPTION
Table 1
PIN
1
2
3
SYMBOL
TCLK
TSER
TCHCLK
TYPE
DESCRIPTION
I
Transmit Clock.
1.544 MHz primary clock.
I
Transmit Serial Data.
Transmit NRZ serial data, sampled on the
falling edge of TCLK.
O
Transmit Channel Clock.
192 kHz clock which pulses high during
the LSB of each channel. Useful for parallel-to-serial conversion of
channel data, locating robbed-bit signaling bits, and for blocking
clocks in DDS applications. See Section 13 for timing details.
O
Transmit Bipolar Data.
Updated on rising edge of TCLK.
I/O
I
Address/Data Bus.
An 8-bit multiplexed address/data bus.
Bus Type Select.
Strap high to select Motorola bus timing; strap
low to select Intel bus timing. This pin controls the function of
RD
(DS), ALE(AS), and
WR
(R/
W
) pins. If BTS=1, then these pins
assume the function listed in parentheses ().
Read Input (Data Strobe).
Chip Select.
Must be low to read or write the port.
Address Latch Enable (Address Strobe).
A positive-going edge
serves to demultiplex the bus.
Write Input (Read/Write).
Receive Link Data.
Updated with either FDL data (ESF) or Fs-bits
(D4) or Z-bits (ZBTSI) one RCLK before the start of a frame. See
Section 13 for timing details.
Signal Ground.
0.0 volts.
Receive Link Clock.
192 kHz clock which pulses high during the
LSB of each channel. Useful for parallel-to-serial conversion of
channel data, locating robbed-bit signaling bits, and for blocking
clocks in DDS applications. See Section 13 for timing details.
Receive Clock.
1.544 MHz primary clock.
3 of 39
4
5
6-13
14
TPOS
TNEG
AD0-AD7
BTS
15
16
17
18
19
RD
(DS)
CS
ALE(AS)
WR
(R/
W
)
I
I
I
I
O
RLINK
20
21
VSS
RLCLK
-
O
22
RCLK
I
DS2141A
PIN
23
SYMBOL
RCHCLK
24
25
RSER
RSYNC
26
27
28
RPOS
RNEG
SYSCLK
29
30
31
32
33
LI_SDI
LI_CLK
LI_CS
RCHBLK
TCHBLK
34
RLOS/LOTC
35
36
INT2
INT1
37
TLCLK
TYPE
DESCRIPTION
O
Receive Channel Clock.
192 kHz clock which pulses high during
the LSB of each channel. Useful for parallel-to-serial conversion of
channel data, locating robbed-bit signaling bits, and for blocking
clocks in DDS applications. See Section 13 for timing details.
O
Receive Serial Data.
Received NRZ serial data; updated on rising
edges of RCLK.
I/O
Receive Sync.
An extracted pulse, one RCLK wide, is output at this
pin which identifies either frame (RCR2.4=0) or multiframe
boundaries (RCR2.4=1). If set to output frame boundaries, then via
RCR2.5, RSYNC can also be set to output double-wide pulses on
signaling frames. If the elastic store is enabled via the CCR1.2, then
this pin can be enabled to be an input via RCR2.3 at which a frame
boundary pulse is applied. See Section 13 for timing details.
I
Receive Bipolar Data Inputs.
Sampled on falling edge of RCLK.
Tie together to receive NRZ data and disable bipolar violation
monitoring circuitry.
I
System Clock.
1.544 MHz or 2.048 MHz clock. Only used when
the elastic store function is enabled via the CCR. Should be tied low
in applications that do not use the elastic store.
O
Serial Port Data for the Line Interface.
Connects directly to the
SDI input pin on the line interface.
O
Serial Port Clock for the Line Interface.
Connects directly to the
SCLK input pin on the line interface.
O
Serial Port Chip Select for the Line Interface.
Connects directly
to the
CS
input pin on the line interface.
O
Receive/Transmit Channel Block.
A user-programmable output
that can be forced high or low during any of the 24 T1 channels.
Useful for blocking clocks to a serial UART or LAPD controller in
application where not all T1 channels are used such as Fractional
T1, 384K bps service, 768K bps, or ISDN-PRI. Also useful for
locating individual channels in drop-and-insert applications. See
Section 13 for timing details.
O
Receive Loss of Sync/Loss of Transmit Clock.
A dual function
output. If CCR1.6=0, then this pin will toggle high when the
synchronizer is searching for the T1 frame and multiframe. If
CCR1.6=1, then this pin will toggle high when the TCLK pin has
not been toggled for 5 ms.
O
Receive Alarm Interrupt 2.
Flags host controller during conditions
defined in Status Register 2. Active low, open drain output.
O
Receive Alarm Interrupt 1.
Flags host controller during alarm
conditions defined in Status Register 1. Active low, open drain
output.
O
Transmit Link Clock.
4 kHz or 2 kHz (ZBTSI) demand clock for
the TLINK input. See Section 13 for timing details.
4 of 39
DS2141A
PIN
38
SYMBOL
TLINK
39
TSYNC
40
VDD
TYPE
DESCRIPTION
I
Transmit Link Data.
If enabled via TCR1.2, this pin will be
sampled during the F-bit time on the falling edge of TCLK for data
insertion into either the FDL stream (ESF) or the Fs-bit position
(D4) or the Z-bit position (ZBTSI). See Section 13 for timing
details.
I/O
Transmit Sync.
A pulse at this pin will establish either frame or
multiframe boundaries for the DS2141A. Via TCR2.2, the DS2141A
can be programmed to output either a frame or multiframe pulse at
this pin. If this pin is set to output pulses at frame boundaries, it can
also be set via TCR2.4 to output double-wide pulses at signaling
frames. See Section 13 for timing details.
-
Positive Supply.
5.0 volts.
DS2141A REGISTER MAP
ADDRESS R/W
REGISTER NAME
20
R/W Status Register 1
21
R/W Status Register 2
22
R/W Receive Information
Register
23
R
Bipolar Violation/ESF
Error Event Count
Register 1
24
R
Bipolar Violation/ESF
Error Event Count
Register 2
25
R
CRC6 Count Register 1
26
R
CRC6 Count Register 2
27
R
Frame Error Count
Register
28
R
Receive FDL Register
29
R/W Receive FDL Match
Register 1
2A
R/W Receive FDL Match
Register 2
2B
R/W Receive Control Register
1
2C
R/W Receive Control Register
2
2D
R/W Receive Mark Register 1
2E
R/W Receive Mark Register 2
2F
R/W Receive Mark Register 3
30
Not Assigned
31
Not Assigned
32
R/W Transmit Channel
Blocking Register 1
33
R/W Transmit Channel
Blocking Register 2
5 of 39
ADDRESS R/W
REGISTER NAME
34
R/W Transmit Channel
Blocking Register 3
35
R/W Transmit Control
Register 1
36
R/W Transmit Control
Register 2
37
R/W Common Control
Register 1
38
R/W Common Control
Register 2
39
R/W Transmit Transparency
Register 1
3A
R/W Transmit Transparency
Register 2
3B
R/W Transmit Transparency
Register 3
3C
R/W Transmit Idle Register 1
3D
R/W Transmit Idle Register 2
3E
R/W Transmit Idle Register 3
3F
R/W Transmit Idle Definition
Register
60
R
Receive Signaling
Register 1
61
R
Receive Signaling
Register 2
62
R
Receive Signaling
Register 3
63
R
Receive Signaling
Register 4
64
R
Receive Signaling
Register 5
RF/无线
