DS2153Q
E1 Single-Chip Transceiver
www.maxim-ic.com
FEATURES
Complete E1 (CEPT) PCM-30/ISDN-PRI
Transceiver Functionality
On-Board Line Interface for Clock/Data
Recovery and Waveshaping
32-Bit or 128-Bit Jitter Attenuator
Generates Line Build-Outs for Both 120Ω
and 75Ω Lines
Frames to FAS, CAS, and CRC4 Formats
Dual On-Board Two-Frame Elastic Store Slip
Buffers That can Connect to Backplanes Up
to 8.192MHz
8-Bit Parallel Control Port That can be Used
on Either Multiplexed or Nonmultiplexed
Buses
Extracts and Inserts CAS Signaling
Detects and Generates Remote and AIS
Alarms
Programmable Output Clocks for Fractional
E1, H0, and H12 Applications
Fully Independent Transmit and Receive
Functionality
Full Access to Both Si and Sa Bits
Three Separate Loopbacks for Testing
Large Counters for Bipolar and Code
Violations, CRC4 Codeword Errors, FAS
Errors, and E Bits
Pin Compatible with DS2151Q T1 Single-
Chip Transceiver
5V Supply; Low-Power CMOS
PIN CONFIGURATION
FUNCTIONAL BLOCKS
LONG & SHORT
HAUL LINE
INTERFACE
FRAMER
PARALLEL CONTROL
PORT
Dallas
DS2153Q
T1SCT
ACTUAL SIZE OF 44-PIN PLCC
TCHCLK
40
39
38
37
36
35
34
33
32
31
30
29
19
20
21
22
23
24
25
26
27
28
RD(DS)
AD7
AD6
AD5
AD4
AD3
AD2
43
AD1
42
6
5
4
3
1
ALE(AS)
WR
(R/W)
RLINK
RLCLK
DVSS
RCLK
RCHCLK
RSER
RSYNC
RLOS/LOTC
SYSCLK
44
41
2
AD0
CS
ELASTIC
STORES
7
8
9
10
11
12
13
14
15
16
17
18
DS2153Q
TSER
TCLK
DVDD
TSYNC
TLINK
TLCLK
TCHBLK
TRING
TVDD
TVSS
TTIP
RTIP
INT1
XTAL1
RCHBLK
RRING
ORDERING INFORMATION
PART
DS2153Q
DS2153Q+
DS2153QN
DS2153QN+
TEMP
RANGE
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
PIN-
PACKAGE
44 PLCC
44 PLCC
44 PLCC
44 PLCC
PLCC
+
Denotes lead-free/RoHS-compliant package.
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
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XTAL2
ACLKI
RVDD
RVSS
INT2
BTS
REV: 01106
DS2153Q
TABLE OF CONTENTS
1
2
3
4
DETAILED DESCRIPTION....................................................................................................4
1.1
1.2
2.1
I
NTRODUCTION
................................................................................................................................ 4
R
EADER
’
S
N
OTE
.............................................................................................................................. 4
DS2153Q R
EGISTER
M
AP
............................................................................................................... 8
PIN DESCRIPTION................................................................................................................6
PARALLEL PORT .................................................................................................................9
CONTROL AND TEST REGISTERS...................................................................................10
4.1
4.2
4.3
4.4
4.5
L
OCAL
L
OOPBACK
......................................................................................................................... 17
R
EMOTE
L
OOPBACK
...................................................................................................................... 17
F
RAMER
L
OOPBACK
...................................................................................................................... 17
A
UTOMATIC
A
LARM
G
ENERATION
................................................................................................... 17
P
OWER
-U
P
S
EQUENCE
................................................................................................................. 17
CRC4 S
YNC
C
OUNTER
................................................................................................................. 20
BPV
OR
C
ODE
V
IOLATION
C
OUNTER
............................................................................................. 26
CRC4 E
RROR
C
OUNTER
............................................................................................................... 27
E-B
IT
C
OUNTER
............................................................................................................................ 27
FAS B
IT
E
RROR
C
OUNTER
............................................................................................................ 28
5
6
STATUS AND INFORMATION REGISTERS ......................................................................18
5.1
6.1
6.2
6.3
6.4
ERROR COUNT REGISTERS.............................................................................................26
7 SA DATA LINK CONTROL AND OPERATION ..................................................................29
8 SIGNALING OPERATION...................................................................................................30
9 TRANSMIT IDLE REGISTERS............................................................................................32
10 CLOCK BLOCKING REGISTERS....................................................................................33
11 ELASTIC STORES OPERATION.....................................................................................35
12 ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION .................................36
13 LINE INTERFACE FUNCTIONS.......................................................................................39
13.1
13.2
13.3
R
ECEIVE
C
LOCK AND
D
ATA
R
ECOVERY
....................................................................................... 40
T
RANSMIT
W
AVESHAPING AND
L
INE
D
RIVING
.............................................................................. 41
J
ITTER
A
TTENUATOR
.................................................................................................................. 42
14
15
16
17
TIMING DIAGRAMS .........................................................................................................46
DC CHARACTERISTICS..................................................................................................52
AC CHARACTERISTICS..................................................................................................53
PACKAGE INFORMATION..............................................................................................60
44-P
IN
PLCC (56-G4003-001).................................................................................................. 60
17.1
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DS2153Q
LIST OF FIGURES
Figure 1-1. DS2153Q Block Diagram ......................................................................................................... 5
Figure 13-1. External Analog Connections............................................................................................... 43
Figure 13-2. Jitter Tolerance .................................................................................................................... 44
Figure 13-3. Transmit Waveform Template .............................................................................................. 44
Figure 13-4. Jitter Attenuation .................................................................................................................. 45
Figure 14-1. Receive Side Timing ............................................................................................................ 46
Figure 14-2. Receive Side Boundary Timing (with Elastic Stores Disabled) ............................................ 46
Figure 14-3. 1.544MHz Boundary Timing with Elastic Store(s) Disabled ................................................. 47
Figure 14-4. 2.048MHz Boundary Timing with Elastic Store(s) Enabled.................................................. 47
Figure 14-5. Transmit Side Timing ........................................................................................................... 48
Figure 14-6. Transmit Side Boundary Timing ........................................................................................... 48
Figure 14-7. G.802 Timing........................................................................................................................ 49
Figure 14-8. Synchronization Flowchart ................................................................................................... 50
Figure 14-9. Transmit Data Flow .............................................................................................................. 51
Figure 16-1. Intel Bus Read AC Timing.................................................................................................... 54
Figure 16-2. Intel Bus Write AC Timing .................................................................................................... 54
Figure 16-3. Motorola Bus AC Timing ...................................................................................................... 55
Figure 16-4. Receive Side AC Timing ...................................................................................................... 57
Figure 16-5. Transmit Side AC Timing ..................................................................................................... 59
LIST OF TABLES
Table 4-1. Sync/Resync Criteria............................................................................................................... 11
Table 5-1. Alarm Set and Clear Criteria ................................................................................................... 22
Table 13-1. Source of RCLK Upon RCL................................................................................................... 40
Table 13-2. LBO Select in LICR ............................................................................................................... 41
Table 13-3. Transformer Specifications.................................................................................................... 41
Table 13-4. Crystal Selection Guidelines ................................................................................................. 42
Table 15-1. Recommended DC Characteristics ....................................................................................... 52
Table 15-2. Capacitance .......................................................................................................................... 52
Table 15-3. DC Characteristics ................................................................................................................ 52
Table 16-1. AC Characteristics—Parallel Port ......................................................................................... 53
Table 16-2. AC Characteristics—Receive Side ........................................................................................ 56
Table 16-3. AC Characteristics—Transmit Side ....................................................................................... 58
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DS2153Q
1 DETAILED DESCRIPTION
The DS2153Q E1 single-chip transceiver (SCT) contains all the necessary functions for connection to E1
lines. The on-board clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to a NRZ serial
stream. The DS2153Q automatically adjusts to E1 22 AWG (0.6mm) twisted-pair cables from 0 to 1.5km.
The device can generate the necessary G.703 waveshapes for both 75Ω and 120Ω cables. The on-board
jitter attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data
paths. The framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It
is also used for extracting and inserting signaling data, Si, and Sa-bit information. The device contains a
set of 71 8-bit internal registers that the user can access to control the operation of the unit. Quick access
via the parallel control port allows a single micro to handle many E1 lines. The device fully meets all the
latest E1 specifications, including ITU G.703, G.704, G.706, G.823, and I.431 as well as ETSI 300 011,
300 233, TBR 12 and TBR 13.
1.1 Introduction
The analog AMI waveform off of the E1 line is transformer coupled into the RRING and RTIP pins of
the DS2153Q. The device recovers clock and data from the analog signal and passes it through the jitter
attenuation mux to the receive side framer where the digital serial stream is analyzed to locate the framing
pattern. If needed, the receive side elastic store can be enabled in order to absorb the phase and frequency
differences between the recovered E1 data stream and an asynchronous backplane clock which is
provided at the SYSCLK input.
The transmit side of the DS2153Q is totally independent from the receive side in both the clock
requirements and characteristics. The transmit formatter will provide the necessary data overhead for E1
transmission. Once the data stream has been prepared for transmission, it is sent via the jitter attenuation
mux to the waveshaping and line driver functions. The DS2153Q will drive the E1 line from the TTIP
and TRING pins via a coupling transformer.
1.2 Reader’s Note
This data sheet assumes a particular nomenclature of the E1 operating environment. There are 32 8-bit
time slots in E1 systems that are numbered 0 to 31. Time slot 0 is transmitted first and received first.
These 32 time slots are also referred to as channels with a numbering scheme of 1 to 32. Time slot 0 is
identical to channel 1, time slot 1 is identical to channel 2, and so on. Each time slot (or channel) is made
up of 8 bits numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is the LSB
and is transmitted last. Throughout this data sheet, the following abbreviations are used:
FAS
CAS
MF
Si
CRC4
CCS
Sa
E-bit
Frame Alignment Signal
Channel Associated Signaling
Multiframe
International Bits
Cyclical Redundancy Check
Common Channel Signaling
Additional bits
CRC4 Error bits
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DS2153Q
Figure 1-1. DS2153Q Block Diagram
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