DS21Q58
E1 Quad Transceiver
www.maxim-ic.com
GENERAL DESCRIPTION
The DS21Q58 E1 quad transceiver contains all the
necessary functions for connecting to four E1 lines.
The DS21Q58 is a direct replacement for the
DS21Q50, with the addition of signaling access and
improved interrupt handling. It is composed of a line
interface unit (LIU), framer, and a TDM backplane
interface, and is controlled through an 8-bit parallel
port configured for Intel or Motorola bus operations or
serial port operation.
FEATURES
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Four Complete E1 (CEPT) PCM-30/ISDN-PRI
Transceivers
Pin Compatible with the DS21Q50 and DS21Q59
Short-Haul Line Interfaces
32-Bit or 128-Bit Crystal-Less Jitter Attenuator
Frames to FAS, CAS, and CRC4 Formats
CAS/CCS Signaling Support
4MHz/8MHz/16MHz Clock Synthesizer
Flexible System Clock with Automatic Source
Switching on Loss-of-Clock Source
Two-Frame Elastic-Store Slip Buffer on the
Receive Side
Interleaving PCM Bus Operation Up to
16.384MHz
Configurable Parallel and Serial Port Operation
Detects and Generates Remote and AIS Alarms
Fully Independent Transmit and Receive
Functionality
Four Separate Loopback Functions
PRBS Generation/Detection/Error Counting
3.3V Low-Power CMOS
Large Counters for Bipolar and Code Violations,
CRC4 Codeword Errors, FAS Word Errors, and
E Bits
Eight Additional User-Configurable Output Pins
100-Pin (14mm x 14mm) LQFP Package
APPLICATIONS
DSLAMs
Routers
IMA and WAN Equipment
PIN CONFIGURATION
TOP VIEW
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Dallas
Semiconductor
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DS21Q58
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100
1
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LQFP
ORDERING INFORMATION
PART
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www.maxim-ic.com/telecom
for a complete list of
Telecommunications data sheets, evaluation kits, application
notes, and software downloads.
TEMP RANGE
0°C to +70°C
-40°C to +85°C
PIN-PACKAGE
100 LQFP
100 LQFP
DS21Q58L
DS21Q58LN
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
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REV: 012104
DS21Q58 E1 Quad Transceiver
TABLE OF CONTENTS
1.
2.
3.
4.
4.1
ACRONYMS .......................................................................................................................6
DETAILED DESCRIPTION.................................................................................................6
BLOCK DIAGRAM .............................................................................................................7
PIN DESCRIPTION.............................................................................................................8
P
IN
F
UNCTION
D
ESCRIPTIONS
......................................................................................................12
5.
6.
6.1
6.2
FUNCTIONAL DESCRIPTION .........................................................................................13
HOST INTERFACE PORT................................................................................................14
P
ARALLEL
P
ORT
O
PERATION
.......................................................................................................14
S
ERIAL
P
ORT
O
PERATION
............................................................................................................14
7.
8.
8.1
8.2
8.3
8.4
8.5
REGISTER MAP...............................................................................................................16
CONTROL, ID, AND TEST REGISTERS .........................................................................17
P
OWER
-U
P
S
EQUENCE
................................................................................................................18
F
RAMER
L
OOPBACK
....................................................................................................................21
A
UTOMATIC
A
LARM
G
ENERATION
.................................................................................................22
R
EMOTE
L
OOPBACK
....................................................................................................................22
L
OCAL
L
OOPBACK
.......................................................................................................................23
9.
9.1
9.2
STATUS AND INFORMATION REGISTERS ...................................................................27
I
NTERRUPT
H
ANDLING
.................................................................................................................28
CRC4 S
YNC
C
OUNTER
................................................................................................................29
10.
ERROR COUNT REGISTERS..........................................................................................34
BPV
OR
CV C
OUNTER
.............................................................................................................34
CRC4 E
RROR
C
OUNTER
..........................................................................................................34
E-B
IT
/PRBS B
IT
-E
RROR
C
OUNTER
..........................................................................................35
FAS E
RROR
C
OUNTER
.............................................................................................................35
R
ECEIVE
S
IGNALING
.................................................................................................................36
T
RANSMIT
S
IGNALING
...............................................................................................................36
CAS O
PERATION
.....................................................................................................................36
10.1
10.2
10.3
10.4
11.
SIGNALING OPERATION................................................................................................36
11.1
11.2
11.3
12.
13.
14.
15.
16.
17.
18.
19.
20.
DS0 MONITORING FUNCTION .......................................................................................37
PRBS GENERATION AND DETECTION.........................................................................39
SYSTEM CLOCK INTERFACE ........................................................................................40
TRANSMIT CLOCK SOURCE..........................................................................................41
IDLE CODE INSERTION ..................................................................................................41
PER-CHANNEL LOOPBACK ..........................................................................................42
ELASTIC STORE OPERATION .......................................................................................42
ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION..................................43
USER-CONFIGURABLE OUTPUTS ................................................................................45
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DS21Q58 E1 Quad Transceiver
21.
LINE INTERFACE UNIT ...................................................................................................47
R
ECEIVE
C
LOCK AND
D
ATA
R
ECOVERY
.....................................................................................47
Termination ...........................................................................................................................................47
21.1.1
21.1
21.2
21.3
21.4
21.4.1
21.4.2
R
ECEIVE
M
ONITOR
M
ODE
.........................................................................................................48
T
RANSMIT
W
AVESHAPING AND
L
INE
D
RIVING
.............................................................................49
J
ITTER
A
TTENUATORS
..............................................................................................................51
Clock and Data Jitter Attenuators .........................................................................................................51
Undedicated Clock Jitter Attenuator .....................................................................................................52
22.
23.
24.
CODE MARK INVERSION (CMI) .....................................................................................53
INTERLEAVED PCM BUS OPERATION .........................................................................55
FUNCTIONAL TIMING DIAGRAMS.................................................................................57
R
ECEIVE
..................................................................................................................................57
T
RANSMIT
................................................................................................................................59
24.1
24.2
25.
26.
OPERATING PARAMETERS...........................................................................................62
AC TIMING PARAMETERS AND DIAGRAMS ................................................................63
M
ULTIPLEXED
B
US
AC C
HARACTERISTICS
.................................................................................63
N
ONMULTIPLEXED
B
US
AC C
HARACTERISTICS
..........................................................................66
S
ERIAL
P
ORT
...........................................................................................................................68
R
ECEIVE
AC C
HARACTERISTICS
...............................................................................................69
T
RANSMIT
AC C
HARACTERISTICS
.............................................................................................71
S
PECIAL
M
ODES
AC C
HARACTERISTICS
....................................................................................72
26.1
26.2
26.3
26.4
26.5
26.6
27.
28.
PACKAGE INFORMATION..............................................................................................73
REVISION HISTORY ........................................................................................................74
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DS21Q58 E1 Quad Transceiver
LIST OF FIGURES
Figure 3-1. Block Diagram ....................................................................................................................... 7
Figure 6-1. Serial Port Operation Mode 1 ...............................................................................................14
Figure 6-2. Serial Port Operation Mode 2 ...............................................................................................15
Figure 6-3. Serial Port Operation Mode 3 ...............................................................................................15
Figure 6-4. Serial Port Operation Mode 4 ...............................................................................................15
Figure 21-1 Typical Monitor Port Application ..........................................................................................48
Figure 21-2. External Analog Connections (Basic Configuration) ...........................................................49
Figure 21-3. External Analog Connections (Protected Interface) ............................................................50
Figure 21-4. Transmit Waveform Template ............................................................................................51
Figure 21-5. Jitter Tolerance...................................................................................................................52
Figure 21-6. Jitter Attenuation ................................................................................................................52
Figure 22-1. CMI Coding ........................................................................................................................53
Figure 22-2. Example of CMI Code Violation..........................................................................................54
Figure 23-1. IBO Configuration Using Two DS21Q58 Transceivers (Eight E1 Lines)..............................56
Figure 24-1. Receive Frame and Multiframe Timing ...............................................................................57
Figure 24-2. Receive Boundary Timing (With Elastic Store Disabled).....................................................57
Figure 24-3. Receive Boundary Timing (With Elastic Store Enabled) .....................................................57
Figure 24-4. Receive Interleave Bus Operation ......................................................................................58
Figure 24-5. Transmit Frame and Multiframe Timing ..............................................................................59
Figure 24-6. Transmit Boundary Timing..................................................................................................59
Figure 24-7. Transmit Interleave Bus Operation .....................................................................................59
Figure 24-8. Framer Synchronization Flowchart .....................................................................................60
Figure 24-9. Transmit Data Flow ............................................................................................................61
Figure 26-1. Intel Bus Read AC Timing (PBTS = 0)................................................................................64
Figure 26-2. Intel Bus Write Timing (PBTS = 0)......................................................................................64
Figure 26-3. Motorola Bus AC Timing (PBTS = 1) ..................................................................................65
Figure 26-4. Intel Bus Read Timing (PBTS = 0)......................................................................................66
Figure 26-5. Intel Bus Write Timing (PBTS = 0)......................................................................................67
Figure 26-6. Motorola Bus Read Timing (PBTS = 1)...............................................................................67
Figure 26-7. Motorola Bus Write Timing (PBTS = 1)...............................................................................67
Figure 26-8. Serial Bus Timing (BTS1 = 1, BTS0 = 0) ............................................................................68
Figure 26-9. Receive AC Timing (Receive Elastic Store Disabled) .........................................................69
Figure 26-10. Receive AC Timing (Receive Elastic Store Enabled) ........................................................70
Figure 26-11. Transmit AC Timing (IBO Disabled)..................................................................................71
Figure 26-12. Transmit AC Timing (IBO Enabled) ..................................................................................72
Figure 26-13. NRZ Input AC Timing .......................................................................................................72
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DS21Q58 E1 Quad Transceiver
LIST OF TABLES
Table 4-1. Pin Description (Sorted by Function) ...................................................................................... 8
Table 4-2. Pin Assignments (Sorted by Number)....................................................................................10
Table 4-3. System (Backplane) Interface Pins ........................................................................................12
Table 4-4. Alternate Jitter Attenuator ......................................................................................................12
Table 4-5. Clock Synthesizer..................................................................................................................12
Table 4-6. Parallel Port Control Pins.......................................................................................................12
Table 4-7. Serial Port Control Pins .........................................................................................................13
Table 4-8. Line Interface Pins.................................................................................................................13
Table 4-9. Supply Pins ...........................................................................................................................13
Table 6-1. Bus Mode Select ...................................................................................................................14
Table 7-1. Register Map (Sorted by Address).........................................................................................16
Table 8-1. Sync/Resync Criteria .............................................................................................................19
Table 8-2. G.703 Function ......................................................................................................................24
Table 8-3. Output Modes........................................................................................................................25
Table 9-1. Alarm Criteria ........................................................................................................................29
Table 13-1. Transmit PRBS Mode Select ...............................................................................................39
Table 13-2. Receive PRBS Mode Select ................................................................................................39
Table 14-1. Synthesizer Output Select ...................................................................................................40
Table 14-2. System Clock Selection .......................................................................................................40
Table 20-1. OUTA and OUTB Function Select .......................................................................................46
Table 21-1 Receive Monitor Mode Gain .................................................................................................48
Table 21-2. Line Build-Out Select in LICR ..............................................................................................49
Table 21-3. Transformer Specifications ..................................................................................................49
Table 23-1. IBO System Clock Select.....................................................................................................55
Table 23-2. IBO Device Assignment.......................................................................................................55
Table 26-1. AC Characteristics—Multiplexed Parallel Port .....................................................................63
Table 26-2. AC Characteristics—Nonmultiplexed Parallel Port...............................................................66
Table 26-3. AC Characteristics—Serial Port (BTS1 = 1, BTS0 = 0) ........................................................68
Table 26-4. AC Characteristics—Receive...............................................................................................69
Table 26-5. AC Characteristics—Transmit..............................................................................................71
Table 26-6. AC Characteristics—Special Modes ....................................................................................72
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FPGA/CPLD
