LE
AVAILAB
DS2408
1-Wire 8-Channel Addressable Switch
FEATURES
Eight Channels of Programmable I/O with
Open-Drain Outputs
On-Resistance of PIO Pulldown Transistor
100Ω (max); Off-Resistance 10MΩ (typ)
Individual Activity Latches Capture
Asynchronous State Changes at PIO Inputs for
Interrogation by the Bus Master
Data-Strobe Output to Synchronize PIO Logic
States to External Read/Write Circuitry
Built-in Multidrop Controller Ensures
Compatibility with Other Dallas Semiconductor
1-Wire
®
Net Products
Supports 1-Wire Conditional Search Command
with Response Controlled by Programmable
PIO Conditions
Unique Factory-Lasered 64-Bit Registration
Number Ensures Error-Free Device Selection
and Absolute Part Identity
Communicates to Host with a Single Digital
Signal at 15.3kbps or 100kbps using 1-Wire
Protocol
Operating Range: 2.8V to 5.25V, -40°C to
+85°C
PIN CONFIGURATION
150-mil SO
ORDERING INFORMATION
PART
TEMP RANGE
DS2408S+
-40°C to +85°C
DS2408S+T&R -40°C to +85°C
+Denotes
a lead(Pb)-free package.
T&R = Tape and reel.
PIN-PACKAGE
16 SO
16 SO
Functional Diagrams
The DS2408 is an 8-channel, programmable I/O 1-Wire chip. PIO outputs are configured as open-drain and
provide an on resistance of 100Ω max. A robust PIO channel-access communication protocol ensures that PIO
output-setting changes occur error-free. A data-valid strobe output can be used to latch PIO logic states into
external circuitry such as a D/A converter (DAC) or microcontroller data bus.
DS2408 operation is controlled over the single-conductor 1-Wire bus. Device communication follows the
standard Dallas Semiconductor 1-Wire protocol. Each DS2408 has its own unalterable and unique 64-bit
ROM registration number that is factory lasered into the chip. The registration number guarantees unique
identification and is used to address the device in a multidrop 1-Wire net environment. Multiple DS2408
devices can reside on a common 1-Wire bus and can operate independently of each other. The DS2408 also
supports 1-Wire conditional search capability based on PIO conditions or power-on-reset activity; the
conditions to cause participation in the conditional search are programmable. The DS2408 has an optional V
CC
supply connection. When an external supply is absent, device power is supplied parasitically from the 1-Wire
Pin Configurations appear at end
is present,
bus. When an external supply
of data sheet.
PIO states are maintained in the absence of the 1-Wire bus power
Functional
RSTZ signal is configurable
sheet.
source. The
Diagrams continued at end of data
to serve as either a hard-wired reset for the PIO output or as a strobe
UCSP is a trademark of Maxim Integrated
for external circuitry to indicate that
Products,
write or PIO read has completed.
a PIO
Inc.
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
DESCRIPTION
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-5702; 12/10
ABSOLUTE MAXIMUM RATINGS*
P0 to P7, RSTZ, I/O Voltage to GND
P0 to P7, RSTZ, I/O combined sink current
Operating Temperature Range
Junction Temperature
Storage Temperature Range
Lead temperature (soldering 10s)
Soldering Temperature (reflow)
DS2408
-0.5V, +6V
20mA
-40°C to +85°C
+150°C
-55°C to +125°C
+300°C
+260°C
*
This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= 0V or
≥
V
PUP
, T
A
= -40°C or +85°C.)
PARAMETER
SYMBOL
CONDITIONS
1-Wire Pullup
Standard speed
V
PUP
Voltage
Overdrive speed
Standby Supply
V
CC
at V
PUP,
I
CCS
Current
I/O pin at 0.3V
I/O Pin General Data
1-Wire Pullup
R
PUP
(Notes 1, 2)
Resistance
Input Capacitance
C
IO
(Notes 3, 4)
I/O pin at V
PUP,
Input Load Current
I
L
V
CC
at 0V
High-to-Low
V
TL
(Notes 4, 5, 6)
Switching Threshold
Input-Low Voltage
V
IL
(Notes 1, 7)
Low-to-High
V
TH
(Notes 4, 5, 8)
Switching Threshold
Switching Hysteresis
V
HY
(Notes 9, 4)
Output-Low Voltage
V
OL
(Note 10)
at 4mA
Standard speed, R
PUP
=
2.2kΩ
Overdrive speed, R
PUP
=
Recovery Time
t
REC
2.2kΩ
(Note 1)
Overdrive speed, Directly
prior to reset pulse; R
PUP
= 2.2kΩ
Rising-Edge Hold-off
Standard speed
t
REH
Time (Notes 11, 4)
Overdrive speed
Timeslot Duration
Standard speed
t
SLOT
(Notes 1, 12)
Overdrive speed
MIN
2.8
3.3
TYP
MAX
5.25
5.25
1
2.2
1200
1
UNITS
V
µA
kΩ
pF
µA
V
V
V
V
V
0.5
0.8
0.16
3.2
0.30
3.4
0.73
0.4
5
2
5
0.5
0.5
65
10
5
2
µs
µs
µs
2 of 39
PARAMETER
SYMBOL
CONDITIONS
I/O Pin, 1-Wire Reset, Presence-Detect Cycle
Standard speed, V
PUP
>
4.5V
Reset-Low Time
t
RSTL
(Notes 1, 12)
Standard speed
Overdrive speed
Standard speed
Presence-Detect High
t
PDH
Time (Note 12)
Overdrive speed
Standard speed, V
PUP
>
4.5V
Presence-Detect Fall
t
FPD
Time (Note 13)
Standard speed
Overdrive speed
Standard speed, V
PUP
>
4.5V
Presence-Detect Low
t
PDL
Time (Note 12)
Standard speed
Overdrive speed
Standard speed, V
PUP
>
4.5V
Presence-Detect
t
MSP
Sample Time (Note 1)
Standard speed
Overdrive speed
I/O Pin, 1-Wire Write
Write-0 Low Time
Standard speed
t
W0L
(Notes 1, 12, 14)
Overdrive speed
Write-1 Low Time
Standard speed
t
W1L
(Notes 1, 12, 14)
Overdrive speed
Write Sample Time
Standard speed
(Slave Sampling)
t
SLS
Overdrive speed
(Note 12)
I/O Pin, 1-Wire Read
Read-Low Time
Standard speed
t
RL
(Notes 1, 15)
Overdrive speed
Read-0 Low Time
Standard speed
(Data From Slave)
t
SPD
Overdrive speed
(Note 12)
Read-Sample Time
Standard speed
t
MSR
(Notes 1, 12, 15)
Overdrive speed
P0 to P7, RSTZ Pin
Input-Low Voltage
V
IL
(Notes 1, 7)
V
X
= max (V
PUP
,V
CC
)
Input-High Voltage
V
IH
(Note 1)
Output-Low Voltage
V
OL
(Note 10)
at 4mA
Leakage Current
I
LP
5.25V at the pin
Output Fall Time
t
FPIO
(Notes 4, 16)
Minimum-Sensed
t
PWMIN
(Notes 4, 17)
PIO Pulse
MIN
480
660
53
15
2
1
1
60
60
7
65
68
8
60
8
5
1
15
1.8
5
1
15
1.8
t
RL
+
δ
t
RL
+
δ
TYP
MAX
720
720
80
60
7
5
8
1
240
280
27
75
75
9
120
13
15
1.8
60
8
15 -
δ
1.8 -
δ
60
8
15
1.8
0.30
UNITS
DS2408
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
V
V
V
µA
ns
µs
V
X
- 0.8
5.25
0.4
100
1
1
5
3 of 39
DS2408
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Note 16:
Note 17:
Note 18:
System Requirement
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the
system and 1-Wire recovery times. The specified value here applies to systems with only one
device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an
active pullup such as that found in the DS2480B may be required.
If a 2.2kΩ resistor is used to pull up the data line to V
PUP
, 5µs after power has been applied,
the parasite capacitance does not affect normal communications.
Guaranteed by design—not production tested.
V
TL
and V
TH
are functions of the internal supply voltage, which in parasitic power mode, is a
function of V
PUP
and the 1-Wire recovery times. The V
TH
and V
TL
maximum specifications
are valid at V
PUP
= 5.25V. In any case, V
TL
< V
TH
< V
PUP
.
Voltage below which, during a falling edge on I/O, a logic '0' is detected.
The voltage on I/O needs to be less or equal to V
ILMAX
whenever the master drives the line
low.
Voltage above which, during a rising edge on I/O, a logic '1' is detected.
After V
TH
is crossed during a rising edge on I/O, the voltage on I/O has to drop by V
HY
to be
detected as logic '0'.
The I-V characteristic is linear for voltages less than 1V.
The earliest recognition of a negative edge is possible at t
REH
after V
TH
has been reached
before.
Highlighted numbers are NOT in compliance with the published 1-Wire standards. See
comparison table below.
Interval during the negative edge on I/O at the beginning of a presence detect pulse between
the time at which the voltage is 90% of V
PUP
and the time at which the voltage is 10% of
V
PUP
.
ε
in Figure 14 represents the time required for the pullup circuitry to pull the voltage on I/O
up from V
IL
to V
TH
. The actual maximum duration for the master to pull the line low is
t
W1LMAX
+ t
F
-
ε
and t
W0LMAX
+ t
F
-
ε
respectively.
δ
in Figure 14 represents the time required for the pullup circuitry to pull the voltage on I/O
up from V
IL
to the input high threshold of the bus master. The actual maximum duration for
the master to pull the line low is t
RLMAX
+ t
F
.
Interval during the device-generated negative edge on any PIO pin or the RSTZ pin between
the time at which the voltage is 90% of V
PUP
and the time at which the voltage is 10% of
V
PUP
. PIO pullup resistor = 2.2kΩ.
Width of the narrowest pulse which trips the activity latch (for any PIO pin) or causes a reset
(for the RSTZ pin). For a pulse duration t
PW
: If t
PW
< t
PWMIN(min)
, the pulse will be rejected. If
t
PWMIN(min)
< t
PW
< t
PWMIN(max)
, the pulse may or may not be rejected. If t
PW
> t
PWMIN(max)
the
pulse will be recognized and latched.
Maximum instantaneous pulldown current through all port pins and the RSTZ pin combined.
No requirement for current balance among different pins.
4 of 39
DS2408
STANDARD VALUES
DS2408 VALUES
PARAMETER
STANDARD
OVERDRIVE
STANDARD
OVERDRIVE
NAME
SPEED
SPEED
SPEED
SPEED
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
1)
t
SLOT
(incl. t
REC
)
61µs
(undef.)
7µs
(undef.) 65µs
(undef.)
10µs
(undef.)
t
RSTL
480µs (undef.)
48µs
80µs
660µs
720µs
53µs
80µs
t
PDH
15µs
60µs
2µs
6µs
15µs
60µs
2µs
7µs
t
PDL
60µs
240µs
8µs
24µs
60µs
280µs
7µs
27µs
t
W0L
60µs
120µs
6µs
16µs
60µs
120µs
8µs
13µs
t
SLS
, t
SPD
15µs
60µs
2µs
6µs
15µs
60µs
1.8µs
8µs
1)
Intentional change, longer recovery-time requirement due to modified 1-Wire front end.
PIN DESCRIPTION
PIN
1
2
NAME
N.C.
P0
Not Connected
I/O Pin of Channel 0. Logic input/open-drain output with 100Ω maximum
on-resistance; 0V to 5.25V operating range. Power-on default is
indeterminate. If it is application-critical for the outputs to power up in the
"off" state, the user should attach an appropriate power-on-reset circuit or
supervisor IC to the RSTZ pin.
Optional Power Supply Input. Range 2.8V to 5.25V; must be tied to GND
if not used.
1-Wire Interface. Open-drain, requires external pullup resistor.
Ground
Not Connected
I/O Pin of Channel 7. Same characteristics as P0.
I/O Pin of Channel 6. Same characteristics as P0.
I/O Pin of Channel 5. Same characteristics as P0.
SW configurable PIO reset input (
RST
) or open-drain strobe output
(
STRB
). When configured as
RST
, a LOW input sets all PIO outputs to
the "off" state by setting all bits in the PIO Output Latch State Register.
When configured as
STRB
, an output strobe will occur after a PIO write
(see Channel-Access Write command) or after a PIO Read (see Channel-
Access Read command). The power-on default function of this pin is
RST
.
I/O pin of channel 4; same characteristics as P0
I/O pin of channel 3; same characteristics as P0
I/O pin of channel 2; same characteristics as P0
I/O pin of channel 1; same characteristics as P0
Not connected
Not connected
DESCRIPTION
3
4
5
6
7
8
9
V
CC
I/O
GND
N.C.
P7
P6
P5
10
RSTZ
11
12
13
14
15
16
P4
P3
P2
P1
N.C.
N.C.
5 of 39
