DS25BR400 Quad 2.5 Gbps CML Transceiver with De-Emphasis and Equalization
March 21, 2008
DS25BR400
Quad 2.5 Gbps CML Transceiver with Transmit
De-Emphasis and Receive Equalization
General Description
The DS25BR400 is a quad 250 Mbps – 2.5 Gbps CML
transceiver, or 8-channel buffer, for use in backplane and ca-
ble applications. With operation down to 250 Mbps, the
DS25BR400 can be used in applications requiring both low
and high frequency data rates. Each input stage has a fixed
equalizer to reduce ISI distortion from board traces. The
equalizers are enabled through two control pins. These con-
trol pins provide flexibility in applications where ISI distortion
may vary from one direction to another. All output drivers have
four selectable steps of de-emphasis to compensate for trans-
mission loss. The de-emphasis blocks are also grouped in
fours. In addition, the DS25BR400 also has loopback control
capability on four channels. All the CML drivers have 50Ω
termination to Vcc. All receivers are internally terminated with
differential 100Ω.
Features
■
■
■
■
■
■
■
250 Mbps – 2.5 Gbps low jitter operation
Optional Fixed Input Equalization
Selectable Output De-emphasis
Individual Loopback Controls
On-chip Termination
+3.3V supply
Lead-less eLLP-60 pin package
(9mmx9mmx0.8mm, 0.5mm pitch)
■
−40°C to +85°C Industrial Temperature Range
■
6 kV ESD Rating, HBM
Applications
■
Backplane or cable driver
■
Signal buffering and repeating
Simplified Application Diagram
20194240
© 2008 National Semiconductor Corporation
201942
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DS25BR400
Functional Block Diagram
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DS25BR400
Connection Diagram
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Leadless eLLP-60 Pin Package
(9 mmx9 mmx0.8 mm, 0.5 mm pitch)
Order number DS25BR400TSQ
See NS Package Number SQA060
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DS25BR400
Pin Descriptions
Pin Name
IB_0+
IB_0−
OA_0+
OA_0−
IB_1+
IB_1−
OA_1+
OA_1−
IB_2+
IB_2−
OA_2+
OA_2−
IB_3+
IB_3−
OA_3+
OA_3−
IA_0+
IA_0−
OB_0+
OB_0−
IA_1+
IA_1−
OB_1+
OB_1−
IA_2+
IA_2−
OB_2+
OB_2−
IA_3+
IA_3−
OB_3+
OB_3−
Pin Number
51
52
48
49
43
42
40
39
33
34
36
37
25
24
28
27
58
57
55
54
6
7
3
4
10
9
13
12
18
19
21
22
I/O
I
O
I
O
I
O
I
O
I
O
I
O
I
O
I
O
Description
Inverting and non-inverting differential inputs of port_0. IB_0+ and IB_0− are internally connected
to a reference voltage through a 50Ω resistor. Refer to
Figure 7
Inverting and non-inverting differential outputs of port_0. OA_0+ and OA_0− are connected to
V
CC
through a 50Ω resistor.
Inverting and non-inverting differential inputs of port_1. IB_1+ and IB_1− are internally connected
to a reference voltage through a 50Ω resistor. Refer to
Figure 7
Inverting and non-inverting differential outputs of port_1. OA_1+ and OA_1− are connected to
V
CC
through a 50Ω resistor.
Inverting and non-inverting differential inputs of port_2. IB_2+ and IB_2− are internally connected
to a reference voltage through a 50Ω resistor. Refer to
Figure 7
Inverting and non-inverting differential outputs of port_2. OA_2+ and OA_2− are connected to
V
CC
through a 50Ω resistor.
Inverting and non-inverting differential inputs of port_3. IB_3+ and IB_3− are internally connected
to a reference voltage through a 50Ω resistor. Refer to
Figure 7
Inverting and non-inverting differential outputs of port_3. OA_3+ and OA_3− are connected to
V
CC
through a 50Ω resistor.
Inverting and non-inverting differential inputs of port_0. IA_0+ and IA_0− are internally connected
to a reference voltage through a 50Ω resistor. Refer to
Figure 7
Inverting and non-inverting differential outputs of port_0. OB_0+ and OB_0− are connected to
V
CC
through a 50Ω resistor.
Inverting and non-inverting differential inputs of port_1. IA_1+ and IA_1− are internally connected
to a reference voltage through a 50Ω resistor. Refer to
Figure 7
Inverting and non-inverting differential outputs of port_1. OB_1+ and OB_1− are connected to
V
CC
through a 50Ω resistor.
Inverting and non-inverting differential inputs of port_2. IA_2+ and IA_2− are internally connected
to a reference voltage through a 50Ω resistor. Refer to
Figure 7
Inverting and non-inverting differential outputs of port_2. OB_2+ and OB_2− are connected to
V
CC
through a 50Ω resistor.
Inverting and non-inverting differential inputs of port_3. IA_3+ and IA_3− are internally connected
to a reference voltage through a 50Ω resistor. Refer to
Figure 7
Inverting and non-inverting differential outputs of port_3. OB_3+ and OB_3− are connected to
V
CC
through a 50Ω resistor.
DIFFERENTIAL I/O
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DS25BR400
Pin Name
EQA
EQB
PreA_0
PreA_1
PreB_0
PreB_1
LB0
LB1
LB2
LB3
RSV
POWER
V
CC
Pin Number
60
16
15
1
31
45
46
44
32
30
59
I/O
I
I
I
I
I
I
I
I
I
Description
This pin is active LOW. A logic LOW at EQA enables equalization for input channels IA_0±, IA_1±,
IA_2±, and IA_3±. By default, this pin is internally pulled high and equalization is disabled.
This pin is active LOW. A logic LOW at EQB enables equalization for input channels IB_0±, IB_1±,
IB_2±, and IB_3±. By default, this pin is internally pulled high and equalization is disabled.
PreA_0 and PreA_1 select the output de-emphasis levels (OA_0±, OA_1±, OA_2±, and OA_3±).
PreA_0 and PreA_1 are internally pulled high. Please see
Table 2
for de-emphasis levels.
PreB_0 and PreB_1 select the output de-emphasis levels (OB_0±, OB_1±, OB_2±, and OB_3±).
PreB_0 and PreB_1 are internally pulled high. Please see
Table 2
for de-emphasis levels.
This pin is active LOW. A logic LOW at LB0 enables the internal loopback path from IB_0± to OA_0
±. LB0 is internally pulled high. Please see
Table 1
for more information.
This pin is active LOW. A logic LOW at LB1 enables the internal loopback path from IB_1± to OA_1
±. LB1 is internally pulled high. Please see
Table 1
for more information.
This pin is active LOW. A logic LOW at LB2 enables the internal loopback path from IB_2± to OA_2
±. LB2 is internally pulled high. Please see
Table 1
for more information.
This pin is active LOW. A logic LOW at LB3 enables the internal loopback path from IB_3± to OA_3
±. LB3 is internally pulled high. Please see
Table 1
for more information.
Reserve pin to support factory testing. This pin can be left open, tied to GND, or tied to GND through
an external pull-down resistor.
V
CC
= 3.3V ± 5%.
Each V
CC
pin should be connected to the V
CC
plane through a low inductance path, typically with a
via located as close as possible to the landing pad of the V
CC
pin.
It is recommended to have a 0.01
μF
or 0.1
μF,
X7R, size-0402 bypass capacitor from each V
CC
pin to ground plane.
CONTROL (3.3V LVCMOS)
5, 11, 20, 26,
35, 41, 50,
56
P
GND
2, 8, 14, 17,
23, 29, 38,
47, 53
DAP
P
Ground reference. Each ground pin should be connected to the ground plane through a low
inductance path, typically with a via located as close as possible to the landing pad of the GND pin.
DAP is the metal contact at the bottom side, located at the center of the eLLP-60 pin package. It
should be connected to the GND plane with at least 4 via to lower the ground impedance and
improve the thermal performance of the package.
GND
P
Note:
I = Input, O = Output, P = Power
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