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DS25BR440

3.125 Gbps Quad LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

厂商名称:National Semiconductor(TI )

厂商官网:http://www.ti.com

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DS25BR440 3.125 Gbps Quad LVDS Buffer with Pre-Emphasis and Equalization
February 11, 2008
DS25BR440
3.125 Gbps Quad LVDS Buffer with Transmit Pre-Emphasis
and Receive Equalization
General Description
The DS25BR440 is a 3.125 Gbps Quad LVDS buffer opti-
mized for high-speed signal routing and repeating over lossy
FR-4 printed circuit board backplanes and balanced cables.
Fully differential signal paths ensure exceptional signal in-
tegrity and noise immunity.
The DS25BR440 features two levels of transmit pre-empha-
sis (PE) and two levels of receive equalization (EQ). Both of
these features compensate for interconnect losses and ulti-
mately maximize noise margin. A loss-of-signal (LOS) circuit
monitors each input channel and a unique LOS pin is asserted
when no signal is detected at that input
Wide input common mode range allows the switch to accept
signals with LVDS, CML and LVPECL levels; the output levels
are LVDS. A very small package footprint requires a minimal
space on the board while the flow-through pinout allows easy
board layout. Each differential input and output is internally
terminated with a 100Ω resistor to lower device return losses,
reduce component count and further minimize board space.
Features
DC - 3.125 Gbps low jitter, low skew, low power operation
Pin selectable transmit pre-emphasis and receive
equalization eliminate data dependant jitter
Wide input common mode voltage range allows DC-
coupled interface to LVDS, CML and LVPECL drivers
LOS circuitry detects open inputs fault
Integrated 100Ω input and output terminations
8 kV ESD on LVDS I/O pins protects adjoining
components
Small 6 mm x 6 mm LLP-40 space saving package
Applications
Clock and data buffering and repeating
Copper cable driving and equalization
FR-4 equalization
OC-48 / STM-16
Typical Application
30007303
© 2008 National Semiconductor Corporation
300073
www.national.com
DS25BR440
Ordering Code
NSID
DS25BR440TSQ
Function
Quad Buffer / Repeater
Available Equalization
Levels
Off / On
Available Pre-Emphasis
Levels
Off / On
Block Diagram
30007301
Connection Diagram
30007302
DS25BR440 Pin Diagram
www.national.com
2
DS25BR440
Pin Descriptions
Pin Name
IN0+, IN0- ,
IN1+, IN1-,
IN2+, IN2-,
IN3+, IN3-
OUT0+, OUT0-,
OUT1+, OUT1-,
OUT2+, OUT2-,
OUT3+, OUT3-
EQ0, EQ1,
EQ2, EQ3
PE0, PE1,
PE2, PE3
PWDN0,
PWDN1,
PWDN2,
PWDN3
LOS0, LOS1,
LOS2, LOS3
NC
PWDN
VDD
GND
Pin
Number
1, 2,
4, 5,
6, 7,
9, 10
29, 28,
27, 26,
24, 23,
22, 21
40, 39,
11, 12
31, 20,
19, 18
35,
34,
33,
32
14, 37,
36, 13
17
38
I/O, Type
I, LVDS
Pin Description
Inverting and non-inverting high speed LVDS input pins.
O, LVDS
Inverting and non-inverting high speed LVDS output pins.
I, LVCMOS
I, LVCMOS
I, LVCMOS
Receive equalization level select pins.
Transmit pre-emphasis level select pins.
Channel output power down pins. When the PWDNn is set to L,
the channel output OUTn is in the power down mode. The LOS
circuitry on the corresponding input remains enabled.
Loss Of Signal output pins, LOSn report when an open input fault
condition is detected at the input, INn. These are open drain
outputs. External pull up resistors are required.
NO CONNECT pins. May be left floating.
Device power down pin. When the PWDN is set to L, the device
is in the power down mode. The LOS circuitry is disabled as well.
Power supply pins.
Ground pin and a pad (DAP - die attach pad).
O, LVCMOS
NC
I, LVCMOS
3, 8,
Power
15,25, 30
16, DAP
Power
3
www.national.com
DS25BR440
Absolute Maximum Ratings
(Note 4)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
−0.3V to +4V
LVCMOS Input Voltage
−0.3V to (V
CC
+ 0.3V)
LVCMOS Output Voltage
−0.3V to (V
CC
+ 0.3V)
LVDS Input Voltage
−0.3V to +4V
LVDS Differential Input Voltage
0.0V to +1V
LVDS Output Voltage
−0.3V to (V
CC
+ 0.3V)
LVDS Differential Output Voltage
0.0V to +1V
LVDS Output Short Circuit Current
5 ms
Duration
Junction Temperature
+150°C
Storage Temperature Range
−65°C to +150°C
Lead Temperature Range
Soldering (4 sec.)
+260°C
Maximum Package Power Dissipation at 25°C
SQA Package
2.44W
Derate SQA Package
19.49 mW/°C above +25°C
Package Thermal Resistance
 θ
JA
 θ
JC
ESD Susceptibility
HBM (Note 1)
MM (Note 2)
CDM (Note 3)
Note 1:
Human Body Model, applicable std. JESD22-A114C
Note 2:
Machine Model, applicable std. JESD22-A115-A
Note 3:
Field Induced Charge Device Model, applicable std.
JESD22-C101-C
+26.9°C/W
+3.8°C/W
8 kV
250V
1250V
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Receiver Differential Input
Voltage (V
ID
)
Operating Free Air
Temperature (T
A
)
Min
3.0
0
−40
Typ
3.3
Max
3.6
1
+85
Units
V
V
°C
+25
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 5, 6, 7)
Symbol
V
IH
V
IL
I
IH
I
IL
V
CL
V
OL
V
ID
V
TH
V
TL
V
CMR
Parameter
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Clamp Voltage
Low Level Output Voltage
Input Differential Voltage
Differential Input High Threshold
Differential Input Low Threshold
Common Mode Voltage Range
V
ID
= 100 mV
V
IN
= +3.6V or 0V
V
CC
= 3.6V or 0V
Any LVDS Input Pin to GND
Between IN+ and IN-
V
CM
= +0.05V or V
CC
-0.05V
−100
0.05
±1
1.7
100
V
IN
= 3.6V
V
CC
= 3.6V
V
IN
= GND
V
CC
= 3.6V
I
CL
= −18 mA, V
CC
= 0V
I
OL
= 4 mA
0
0
0
V
CC
-
0.05
±10
Conditions
Min
2.0
GND
0
0
−0.9
0.26
Typ
Max
V
DD
0.8
±10
±10
−1.5
0.4
1
+100
Units
V
V
μA
μA
V
V
V
mV
mV
V
μA
pF
Ω
LVCMOS DC SPECIFICATIONS
LVDS INPUT DC SPECIFICATIONS
I
IN
C
IN
R
IN
Input Current
Input Capacitance
Input Termination Resistor
www.national.com
4
DS25BR440
Symbol
V
OD
ΔV
OD
V
OS
ΔV
OS
I
OS
C
OUT
R
OUT
I
CC
I
CCZ
Parameter
Differential Output Voltage
Change in Magnitude of V
OD
for Complimentary
Output States
Offset Voltage
Change in Magnitude of V
OS
for Complimentary
Output States
Output Short Circuit Current (Note 8)
Output Capacitance
Output Termination Resistor
Supply Current
Power Down Supply Current
R
L
= 100Ω
R
L
= 100Ω
Conditions
Min
250
-35
1.05
-35
Typ
350
Max
450
35
Units
mV
mV
V
mV
mA
mA
pF
Ω
LVDS OUTPUT DC SPECIFICATIONS
1.2
1.375
35
OUT to GND
OUT to V
CC
Any LVDS Output Pin to GND
Between OUT+ and OUT-
PE = OFF, EQ = OFF
PWDN = H
PWDN = L
-35
7
1.2
100
162
55
-55
55
SUPPLY CURRENT
190
63
mA
mA
Note 4:
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 5:
The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 6:
Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except V
OD
and
ΔV
OD
.
Note 7:
Typical values represent most likely parametric norms for V
CC
= +3.3V and T
A
= +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 8:
Output short circuit current (I
OS
) is specified as magnitude only, minus sign indicates direction only.
5
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