DESIGN KIT AVAILABLE
DS26502
T1/E1/J1/64KCC BITS Element
www.maxim-ic.com
GENERAL DESCRIPTION
The DS26502 is a building-integrated timing-
supply (BITS) clock-recovery element. It also
functions as a basic T1/E1 transceiver. The
receiver portion can recover a clock from T1,
E1, 64kHz composite clock (64KCC), and
6312kHz synchronization timing interfaces. In
T1 and E1 modes, the Synchronization Status
Message (SSM) can also be recovered. The
transmit portion can directly interface to T1, E1,
or 64KCC synchronization interfaces as well as
source the SSM in T1 and E1 modes. The
DS26502 can translate between any of the
supported inbound synchronization clock rates to
any supported outbound rate. A separate output
is provided to source a 6312kHz clock. The
device is controlled through a parallel, serial, or
hardware controller port.
FEATURES
G.703 2048kHz Synchronization Interface
Compliant
G.703 64kHz Centralized (Option A) and
Codirectional Timing Interface Compliant
G.703 Appendix II 64kHz and 6312kHz
Japanese Synchronization Interface
Compliant
Interfaces to Standard T1/J1 (1.544MHz) and
E1 (2.048MHz)
Interface to CMI-Coded T1/J1 and E1
Short- and Long-Haul Line Interface
Transmit and Receive T1 and E1 SSM
Messages with Message Validation
T1/E1 Jitter Attenuator with Bypass Mode
Fully Independent Transmit and Receive
Functionality
Internal Software-Selectable Receive- and
Transmit-Side Termination for
75Ω/100Ω/110Ω/120Ω T1, E1, and
Composite Clock Interfaces
Monitor Mode for Bridging Applications
Accepts 16.384MHz, 12.8MHz, 8.192MHz,
4.096MHz, 2.048MHz, or 1.544MHz Master
Clock
64kHz, 8kHz, and 400Hz Outputs in
Composite Clock Mode
8-Bit Parallel Control Port, Multiplexed or
Nonmultiplexed, Intel or Motorola
Serial (SPI) Control Port
Hardware Contr-ol Mode
Provides LOS, AIS, and LOF Indications
Through Hardware Output Pins
Fast Transmitter-Output Disable Through
Device Pin for Protection Switching
IEEE 1149.1 JTAG Boundary Scan
3.3V Supply with 5V Tolerant Inputs and
Outputs
APPLICATIONS
BITS Timing
Rate Conversion
ORDERING INFORMATION
PART
DS26502L
DS26502LN
TEMP RANGE
0°C to +70°C
-40°C to +85°C
PIN-PACKAGE
64 LQFP
64 LQFP
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
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DS26502 T1/E1/J1/64KCC BITS Element
TABLE OF CONTENTS
1.
1.1
1.2
1.3
1.4
1.5
1.6
FEATURES .......................................................................................................................7
G
ENERAL
.....................................................................................................................................7
L
INE
I
NTERFACE
...........................................................................................................................7
J
ITTER
A
TTENUATOR
(T1/E1 M
ODES
O
NLY
)
..................................................................................7
F
RAMER
/F
ORMATTER
...................................................................................................................8
T
EST AND
D
IAGNOSTICS
...............................................................................................................8
C
ONTROL
P
ORT
............................................................................................................................8
2.
3.
4.
4.1
4.2
4.3
4.4
4.5
4.6
4.7
SPECIFICATIONS COMPLIANCE ...................................................................................9
BLOCK DIAGRAMS .......................................................................................................11
PIN FUNCTION DESCRIPTION .....................................................................................14
T
RANSMIT
PLL
...........................................................................................................................14
T
RANSMIT
S
IDE
..........................................................................................................................14
R
ECEIVE
S
IDE
............................................................................................................................15
C
ONTROLLER
I
NTERFACE
............................................................................................................16
JTAG.........................................................................................................................................21
L
INE
I
NTERFACE
.........................................................................................................................21
P
OWER
......................................................................................................................................22
5.
6.
6.1
6.2
6.3
6.4
6.5
6.6
6.7
PINOUT...........................................................................................................................23
HARDWARE CONTROLLER INTERFACE....................................................................26
T
RANSMIT
C
LOCK
S
OURCE
.........................................................................................................26
I
NTERNAL
T
ERMINATION
..............................................................................................................26
L
INE
B
UILD
-O
UT
.........................................................................................................................27
R
ECEIVER
O
PERATING
M
ODES
....................................................................................................27
T
RANSMITTER
O
PERATING
M
ODES
..............................................................................................28
MCLK P
RE
-S
CALER
...................................................................................................................28
O
THER
H
ARDWARE
C
ONTROLLER
M
ODE
F
EATURES
....................................................................29
7.
7.1
7.2
PROCESSOR INTERFACE ............................................................................................30
P
ARALLEL
P
ORT
F
UNCTIONAL
D
ESCRIPTION
................................................................................30
SPI S
ERIAL
P
ORT
I
NTERFACE
F
UNCTIONAL
D
ESCRIPTION
............................................................30
Clock Phase and Polarity ..................................................................................................................... 30
Bit Order............................................................................................................................................... 30
Control Byte ......................................................................................................................................... 30
Burst Mode........................................................................................................................................... 30
Register Writes..................................................................................................................................... 31
Register Reads .................................................................................................................................... 31
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.3
7.3.1
7.3.2
7.3.3
R
EGISTER
M
AP
...........................................................................................................................32
Power-Up Sequence ............................................................................................................................ 34
Test Reset Register ............................................................................................................................. 34
Mode Configuration Register ............................................................................................................... 35
7.4
7.5
7.6
7.7
I
NTERRUPT
H
ANDLING
................................................................................................................38
S
TATUS
R
EGISTERS
....................................................................................................................38
I
NFORMATION
R
EGISTERS
...........................................................................................................39
I
NTERRUPT
I
NFORMATION
R
EGISTERS
.........................................................................................39
8.
8.1
T1 FRAMER/FORMATTER CONTROL REGISTERS ....................................................40
T1 C
ONTROL
R
EGISTERS
............................................................................................................40
9.
9.1
E1 FRAMER/FORMATTER CONTROL REGISTERS....................................................46
E1 C
ONTROL
R
EGISTERS
...........................................................................................................46
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DS26502 T1/E1/J1/64KCC BITS Element
9.2
E1 I
NFORMATION
R
EGISTERS
......................................................................................................48
10.
11.
11.1
11.2
11.3
I/O PIN CONFIGURATION OPTIONS ............................................................................52
T1 SYNCHRONIZATION STATUS MESSAGE ..............................................................55
T1 B
IT
-O
RIENTED
C
ODE
(BOC) C
ONTROLLER
............................................................................55
T
RANSMIT
BOC
.........................................................................................................................55
R
ECEIVE
BOC
...........................................................................................................................56
12.
12.1
12.2
E1 SYNCHRONIZATION STATUS MESSAGE ..............................................................64
S
A
/S
I
B
IT
A
CCESS
B
ASED ON
CRC4 M
ULTIFRAME
......................................................................64
A
LTERNATE
S
A
/S
I
B
IT
A
CCESS
B
ASED ON
D
OUBLE
-F
RAME
.........................................................74
13.
13.1
13.2
LINE INTERFACE UNIT (LIU) ........................................................................................77
LIU O
PERATION
.........................................................................................................................78
LIU R
ECEIVER
...........................................................................................................................78
Receive Level Indicator........................................................................................................................ 78
Receive G.703 Section 13 Synchronization Signal ............................................................................. 79
Monitor Mode ....................................................................................................................................... 79
13.2.1
13.2.2
13.2.3
13.3
13.3.1
13.3.2
13.3.3
13.3.4
LIU T
RANSMITTER
.....................................................................................................................79
Transmit Short-Circuit Detector/Limiter................................................................................................ 80
Transmit Open-Circuit Detector ........................................................................................................... 80
Transmit BPV Error Insertion ............................................................................................................... 80
Transmit G.703 Section 10 Synchronization Signal (E1 Mode)........................................................... 80
13.4
13.5
13.6
13.7
13.8
MCLK P
RE
-S
CALER
..................................................................................................................80
J
ITTER
A
TTENUATOR
..................................................................................................................80
CMI (C
ODE
M
ARK
I
NVERSION
) O
PTION
.......................................................................................81
LIU C
ONTROL
R
EGISTERS
..........................................................................................................82
R
ECOMMENDED
C
IRCUITS
..........................................................................................................90
14.
15.
15.1
15.2
LOOPBACK CONFIGURATION.....................................................................................95
64KHZ SYNCHRONIZATION INTERFACE....................................................................96
R
ECEIVE
64
K
H
Z
S
YNCHRONIZATION
I
NTERFACE
O
PERATION
.......................................................96
T
RANSMIT
64
K
H
Z
S
YNCHRONIZATION
I
NTERFACE
O
PERATION
.....................................................97
16.
16.1
16.2
6312KHZ SYNCHRONIZATION INTERFACE................................................................98
R
ECEIVE
6312
K
H
Z
S
YNCHRONIZATION
I
NTERFACE
O
PERATION
...................................................98
T
RANSMIT
6312
K
H
Z
S
YNCHRONIZATION
I
NTERFACE
O
PERATION
.................................................98
17.
17.1
17.2
JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT ...................99
I
NSTRUCTION
R
EGISTER
...........................................................................................................103
T
EST
R
EGISTERS
.....................................................................................................................104
Boundary Scan Register .................................................................................................................... 104
Bypass Register ................................................................................................................................. 104
Identification Register......................................................................................................................... 104
17.2.1
17.2.2
17.2.3
18.
18.1
FUNCTIONAL TIMING DIAGRAMS .............................................................................107
P
ROCESSOR
I
NTERFACE
...........................................................................................................107
Parallel Port Mode.............................................................................................................................. 107
SPI Serial Port Mode.......................................................................................................................... 107
18.1.1
18.1.2
19.
20.
20.1
20.2
20.3
OPERATING PARAMETERS .......................................................................................110
AC TIMING PARAMETERS AND DIAGRAMS ............................................................112
M
ULTIPLEXED
B
US
...................................................................................................................112
N
ONMULTIPLEXED
B
US
.............................................................................................................115
S
ERIAL
B
US
.............................................................................................................................118
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DS26502 T1/E1/J1/64KCC BITS Element
20.4
20.5
R
ECEIVE
S
IDE
AC C
HARACTERISTICS
.......................................................................................120
T
RANSMIT
S
IDE
AC C
HARACTERISTICS
.....................................................................................122
21.
22.
22.1
REVISION HISTORY ....................................................................................................124
PACKAGE INFORMATION ..........................................................................................125
64-P
IN
LQFP (56-G4019-001).................................................................................................125
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DS26502 T1/E1/J1/64KCC BITS Element
LIST OF FIGURES
Figure 3-1. Block Diagram ........................................................................................................................11
Figure 3-2. Loopback Mux Diagram (T1/E1 Modes Only) ........................................................................12
Figure 3-3. Transmit PLL Clock Mux Diagram..........................................................................................12
Figure 3-4. Master Clock PLL Diagram ....................................................................................................13
Figure 13-1. Basic Network Connection ...................................................................................................77
Figure 13-2. Typical Monitor Application ..................................................................................................79
Figure 13-3. CMI Coding ..........................................................................................................................81
Figure 13-4. Software-Selected Termination, Metallic Protection.............................................................90
Figure 13-5. Software-Selected Termination, Longitudinal Protection .....................................................91
Figure 13-6. E1 Transmit Pulse Template ................................................................................................92
Figure 13-7. T1 Transmit Pulse Template ................................................................................................92
Figure 13-8. Jitter Tolerance (T1 Mode) ...................................................................................................93
Figure 13-9. Jitter Tolerance (E1 Mode)...................................................................................................93
Figure 13-10. Jitter Attenuation (T1 Mode)...............................................................................................94
Figure 13-11. Jitter Attenuation (E1 Mode) ..............................................................................................94
Figure 15-1. 64kHz Composite Clock Mode Signal Format......................................................................96
Figure 17-1. JTAG Functional Block Diagram ..........................................................................................99
Figure 17-2. TAP Controller State Diagram............................................................................................102
Figure 18-1. SPI Serial Port Access, Read Mode, CPOL = 0, CPHA = 0...............................................107
Figure 18-2. SPI Serial Port Access, Read Mode, CPOL = 1, CPHA = 0...............................................107
Figure 18-3. SPI Serial Port Access, Read Mode, CPOL = 0, CPHA = 1...............................................107
Figure 18-4. SPI Serial Port Access, Read Mode, CPOL = 1, CPHA = 1...............................................108
Figure 18-5. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 0...............................................108
Figure 18-6. SPI Serial Port Access, Write Mode, CPOL = 1, CPHA = 0...............................................108
Figure 18-7. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 1...............................................109
Figure 18-8. SPI Serial Port Access, Write Mode, CPOL = 1, CPHA = 1...............................................109
Figure 20-1. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 00)...............................................................113
Figure 20-2. Intel Bus Write Timing (BTS = 0 / BIS[1:0] = 00)................................................................113
Figure 20-3. Motorola Bus Timing (BTS = 1 / BIS[1:0] = 00) ..................................................................114
Figure 20-4. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 01)................................................................116
Figure 20-5. Intel Bus Write Timing (BTS = 0 / BIS[1:0] = 01)................................................................116
Figure 20-6. Motorola Bus Read Timing (BTS = 1 / BIS[1:0] = 01) ........................................................117
Figure 20-7. Motorola Bus Write Timing (BTS = 1 / BIS[1:0] = 01).........................................................117
Figure 20-8. SPI Interface Timing Diagram, CPHA = 0, BIS[1:0] = 10 ...................................................119
Figure 20-9. SPI Interface Timing Diagram, CPHA = 1, BIS[1:0] = 10 ...................................................119
Figure 20-10. Receive Timing, T1, E1, 64KCC Mode ............................................................................121
Figure 20-11. Transmit Timing, T1, E1, 64KCC Mode ...........................................................................123
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