DS5000FP
Soft Microprocessor Chip
www.maxim-ic.com
FEATURES
§
8051-compatible microprocessor adapts to its
task
-
Accesses between 8kB and 64kB of
nonvolatile SRAM
-
In-system programming via on-chip serial
port
-
Can modify its own program or data
memory
-
Accesses memory on a separate Byte-
wide bus
Crashproof operation
-
Maintains all nonvolatile resources for
over 10 years
-
Power-fail Reset
-
Early Warning Power-fail Interrupt
-
Watchdog Timer
-
User-supplied lithium battery backs user
SRAM for program/data storage
Software security
-
Executes encrypted programs to prevent
observation
-
Security lock prevents download
-
Unlocking destroys contents
Fully 8051-compatible
-
128 bytes scratchpad RAM
-
Two timer/counters
-
On-chip serial port
-
32 parallel I/O port pins
PIN ASSIGNMENT
BA11
P0.5/AD5
CE2
P0.6/AD6
BA10
P0.7/AD7
CE1
EA
NC
BD7
ALE
BD6
PSEN
BD5
P2.7/A15
BD4
P0.4/AD4
NC
NC
BA9
P0.3/AD3
BA8
P0.2/AD2
BA13
P0.1/AD1
R/W
P0.0/AD0
VCC0
VCC
VCC
P1.0
BA14
P1.1
BA12
P1.2
BA7
P1.3
NC
NC
BA6
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
§
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DS5000FP
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P2.6/A14
NC
NC
BD3
P2.5/A13
BD2
P2.4/A12
BD1
P2.3/A11
BD0
VLI
GND
GND
P2.2/A10
P2.1/A9
P2.0/A8
XTAL1
XTAL2
P3.7/RD
P3.6/WR
P3.5/T1
NC
NC
P3.4/T0
§
Note:
Some revisions of this device may incorporate deviations from published specifications known
as errata. Multiple revisions of any device may be simultaneously available through various sales
channels. For information about device errata, click here:
http://dbserv.maxim-ic.com/errata.cfm.
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112299
P1.4
BA5
P1.5
BA4
P1.6
BA3
P1.7
NC
BA2
RST
BA1
P3.0/RXD
BA0
P3.1/TXD
P3.2/INT0
P3.3/INT1
§
DS5000FP
DESCRIPTION
The DS5000FP Soft Microprocessor Chip is an 8051-compatible processor based on NV RAM
technology. It is substantially more flexible than a standard 8051, yet provides full compatibility with the
8051 instruction set, timers, serial port, and parallel I/O ports. By using NV RAM instead of ROM, the
user can program and then reprogram the microcontroller while in-system. The application software can
even change its own operation, which allows frequent software upgrades, adaptive programs, customized
systems, etc. In addition, by using NV SRAM, the DS5000FP is ideal for data-logging applications and it
connects easily to a Dallas real-time clock for time stamp and date.
The DS5000FP provides the benefits of NV RAM without using I/O resources. It uses a non-multiplexed
Byte-wide address and data bus for memory access. This bus can perform all memory access and
provides decoded chip enables for SRAM. This leaves the 32 I/O port pins free for application use. The
DS5000FP uses ordinary SRAM and battery backs the memory contents with a user’s external lithium
cell. Data is maintained for over 10 years with a very small lithium cell. A DS5000FP also provides
crashproof operation in portable systems or systems with unreliable power. These features include the
ability to save the operating state, Power-fail Reset, Power-fail Interrupt, and Watchdog Timer.
A user loads programs into the DS5000FP via its on-chip Serial Bootstrap Loader. This function
supervises the loading of code into NV RAM, validates it, then becomes transparent to the user. Software
can be stored in an 8-kbyte or 32-kbyte CMOS SRAM. Using its internal Partitioning, the DS5000FP will
divide this common RAM into user programmable code and data segments. This Partition can be
selected at program loading time, but can be modified anytime later. It will decode memory access to the
SRAM, communicate via its Byte-wide bus and write-protect the memory portion designated as ROM.
Combining program and data storage in one device saves board space and cost. The DS5000FP can also
access a second 32 kbytes of NV RAM but this area is restricted to data memory. For a user that wants a
pre-constructed module using the DS5000FP, RAM, lithium cell, and optional real time clock; the
DS2250(T) and DS5000(T) are available and described in separate data sheets. More details are also
contained in the User’s Guide section of the Secure Microcontroller Data Book.
ORDERING INFORMATION
The following devices are available as standard products from Dallas Semiconductor:
PART #
DS5000FP-16
DESCRIPTION
80-pin QFP, Max. clock speed 16 MHz, 0° to 70°C operation
Operating information is contained in the User’s Guide section of the Secure Microcontroller Data Book.
This data sheet provides ordering information, pin-out, and electrical specifications.
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DS5000FP
DS5000FP BLOCK DIAGRAM
Figure 1
3 of 22
DS5000FP
PIN DESCRIPTION
PIN
DESCRIPTION
15, 17, 19,
P1.0 - P1.7.
General purpose I/O Port 1.
21, 25, 27,
29, 31
34
36
38
39
40
41
44
45
46
47, 48
52, 53
RST -
Active high reset input. A logic 1 applied to this pin will activate a reset state. This
pin is pulled down internally so this pin can be left unconnected if not used.
P3.0 RXD.
General purpose I/O port pin 3.0. Also serves as the receive signal for the on
board UART. This pin should not be connected directly to a PC COM port.
P3.1 TXD.
General purpose I/O port pin 3.1. Also serves as the transmit signal for the on
board UART. This pin should not be connected directly to a PC COM port.
P3.2
INT0
.
General purpose I/O port pin 3.2. Also serves as the active low External
Interrupt 0.
P3.3
INT1
.
General purpose I/O port pin 3.3. Also serves as the active low External
Interrupt 1.
P3.4 T0.
General purpose I/O port pin 3.4. Also serves as the Timer 0 input.
P3.5 T1.
General purpose I/O port pin 3.5. Also serves as the Timer 1 input.
P3.6
WR
.
General purpose I/O port pin. Also serves as the write strobe for Expanded bus
operation.
P3.7
RD
.
General purpose I/O port pin. Also serves as the read strobe for Expanded bus
operation.
XTAL2, XTAL1.
Used to connect an external crystal to the internal oscillator. XTAL1 is
the input to an inverting amplifier and XTAL2 is the output.
GND.
Logic ground.
49, 50, 51,
P2.0-P2.7.
General purpose I/O Port 2. Also serves as the MSB of the Expanded Address
56, 58, 60, bus.
64, 66
68
-
Program Store Enable. This active low signal is used to enable an external
program memory when using the Expanded bus. It is normally an output and should be
unconnected if not used.
PSEN
is also used to invoke the Bootstrap Loader. At this time,
PSEN
will be pulled down externally. This should only be done once the DS5000FP is
already in a reset state. The device that pulls down should be open drain since it must not
interfere with
PSEN
under normal operation.
PSEN
70
ALE -
Address Latch Enable. Used to de-multiplex the multiplexed Expanded
Address/Data bus on Port 0. This pin is normally connected to the clock input on a ’373
type transparent latch. When using a parallel programmer, this pin also assumes the
PROG
function for programming pulses.
-
External Access. This pin forces the DS5000FP to behave like an 8031. No internal
memory (or clock) will be available when this pin is at a logic low. Since this pin is pulled
down internally, it should be connected to +5V to use NV RAM. In a parallel
programmer, this pin also serves as V
PP
for super voltage pulses.
EA
73
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DS5000FP
PIN
DESCRIPTION
11, 9, 7, 5,
P0.0-P0.7.
General purpose I/O Port 0. This port is open-drain and can not drive a logic 1.
1, 79, 77, It requires external pullups. Port 0 is also the multiplexed Expanded Address/Data bus.
75
When used in this mode, it does not require pullups.
13, 14
16, 8, 18,
80, 76, 4,
6, 20, 24,
26, 28, 30,
33, 35, 37
V
CC
- +5V
BA14-0.
Byte-wide Address bus bits 14-0. This 15 bit bus is combined with the non-
multiplexed data bus (BD7-0) to access NV SRAM. Decoding is performed on
CE1
and
CE2
. Read/write access is controlled by R/
W
. BA14-0 connect directly to an 8k or 32k
SRAM. If an 8k RAM is used, BA13 and BA14 will be unconnected. Note BA13 and
BA14 are inverted from the true logical address. Also note that BA14 is lithium backed.
71, 69, 67,
BD7-0.
Byte-wide Data bus bits 7-0. This 8-bit bi-directional bus is combined with the
65, 61, 59, non-multiplexed address bus (BA14-0) to access NV SRAM. Decoding is performed on
57, 55
CE1
and
CE2
. Read/write access is controlled by R/W. BD7-0 connect directly to an 8k
or 32k SRAM, and optionally to a Real-time Clock.
10
R/W -
Read/Write. This signal provides the write enable to the SRAMs on the Byte-wide
bus. It is controlled by the memory map and Partition. The blocks selected as Program
(ROM) will be write protected.
-
Chip Enable 1. This is the primary decoded chip enable for memory access on the
Byte-wide bus. It connects to the chip enable input of one SRAM.
CE1
is lithium backed.
It will remain in a logic high inactive state when V
CC
falls below V
LI
.
CE1
74
78
-
Chip Enable 2. This chip enable is provided to bank switch to a second block of
32k bytes of nonvolatile data memory. It connects to the chip enable input of one SRAM
or one lithium-backed peripheral such a DS1283 clock.
CE2
is lithium backed. It will
remain in a logic high inactive state when V
CC
falls below V
LI
.
CE2
12
V
CCO
-
V
CC
Output. This is switched between V
CC
and V
LI
by internal circuits based on
the level of V
CC
. When power is above the lithium input, power will be drawn from V
CC
.
The lithium cell remains isolated from a load. When V
CC
is below V
LI
, the V
CCO
switches
to the V
LI
source. V
CCO
is connected to the V
CC
pin of an SRAM.
V
LI
L -
Lithium Voltage Input. Connect to a lithium cell greater than V
LImin
and no greater
than V
LImax
as shown in the electrical specifications. Nominal value is +3V.
54
2, 3, 22,
NC do not connect.
23, 32, 42,
43, 62, 63,
72
INSTRUCTION SET
The DS5000FP executes an instruction set that is object code compatible with the industry standard 8051
microcontroller. As a result, software development packages such as assemblers and compilers that have
been written for the 8051 are compatible with the DS5000FP. A complete description of the instruction
set and operation are provided in the User’s Guide section of the Secure Microcontroller Data Book.
Also note that the DS5000FP is embodied in the DS5000(T) and DS2250(T) modules. The DS5000(T)
combines the DS5000FP with one SRAM of either 8 or 32 kbytes and a lithium cell. An optional Real
Time Clock is also available in the DS5000T. This is packaged in a 40-pin DIP module. The DS2250(T)
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DSP 与 ARM 处理器
