DS87C530/DS83C530
EPROM/ROM Micro with Real Time Clock
www.dalsemi.com
FEATURES
80C52-compatible
- 8051 instruction set-compatible
- Four 8-bit I/O ports
- Three 16-bit timer/counters
- 256 bytes scratchpad RAM
Large on-chip memory
- 16 kB EPROM (OTP)
- 1 kB extra on-chip SRAM for MOVX
ROMSIZE Feature
- Selects effective on-chip ROM size from
0 to 16kB
- Allows access to entire external memory
map
- Dynamically adjustable by software
- Useful as boot block for external Flash
Nonvolatile Functions
-
On-chip Real Time Clock w/ Alarm
Interrupt
-
Battery backup support of 1 kB SRAM
High-Speed Architecture
- 4 clocks/machine cycle (8051 = 12)
- Runs DC to 33 MHz clock rates
- Single-cycle instruction in 121 ns
- Dual data pointer
- Optional variable length MOVX to access
fast/slow RAM /peripherals
Power Management Mode
- Programmable clock source saves power
- Runs from (crystal/64) or (crystal/1024)
- Provides automatic hardware and software
exit
EMI Reduction Mode disables ALE
Two full-duplex hardware serial ports
High integration controller includes:
- Power-Fail Reset
- Early-Warning Power-Fail Interrupt
- Programmable Watchdog Timer
14 total interrupt sources with 6 external
PACKAGE OUTLINE
7
8
1
47
46
DALLAS
DS87C530
DS83C530
20
21
33
34
52-Pin PLCC
52-Pin CER QUAD
39
27
40
26
DALLAS
DS87C530
DS83C530
52
14
1
13
52-Pin TQFP OUTLINE
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DS87C530/DS83C530
DESCRIPTION
The DS87C530/DS83C530 EPROM/ROM Micro with Real Time Clock is an 8051-compatible
microcontroller based on the Dallas high-speed core. It uses 4 clocks per instruction cycle instead of 12
used by the standard 8051. It also provides a unique mix of peripherals not widely available on other
processors. They include an on-chip Real Time Clock (RTC) and battery back up support for an on-chip
1k x 8 SRAM. The new Power Management Mode allows software to select reduced power operation
while still processing.
A combination of high performance microcontroller core, Real Time Clock, battery backed SRAM, and
power management makes the DS87C530/DS83C530 ideal for instruments and portable applications. It
also provides several peripherals found on other Dallas High-Speed Microcontrollers. These include two
independent serial ports, two data pointers, on-chip power monitor with brown-out detection and a
Watchdog Timer.
Power Management Mode (PMM) allows software to select a slower CPU clock. While default operation
uses four clocks per machine cycle, the PMM runs the processor at 64 or 1024 clocks per cycle. There is a
corresponding drop in power consumption when the processor slows.
The EMI reduction feature allows software to select a reduced emission mode. This disables the ALE
signal when it is unneeded.
The DS83C530 is a factory Mask ROM version of the DS87C530 designed for high-volume, cost-
sensitive applications. It is identical in all respects to the DS87C530, except that the 16 kB of EPROM is
replaced by a user-supplied application program. All references to features of the DS87C530 will apply to
the DS83C530, with the exception of EPROM-specific features where noted. Please contact your local
Dallas Semiconductor sales representative for ordering information.
Note: The DS87C530/DS83C530 is a monolithic device. A user must supply an external battery or super-
cap and a 32.768 kHz timekeeping crystal to have permanently powered timekeeping or nonvolatile
RAM. The DS87C530/DS83C530 provides all the support and switching circuitry needed to manage
these resources.
ORDERING INFORMATION
PART NUMBER
DS87C530-QCL
DS87C530-QNL
DS87C530-KCL
DS87C530-ECL
DS87C530-ENL
DS83C530-QCL
DS83C530-QNL
DS83C530-ECL
DS83C530-ENL
PACKAGE
52-pin PLCC
52-pin PLCC
52-pin windowed CERQUAD
52-pin TQFP
52-pin TQFP
52-pin windowed CERQUAD
52-pin TQFP
52-pin TQFP
52-pin TQFP
MAX. CLOCK
SPEED
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
TEMPERATURE RANGE
0°C to 70°C
-40°C to +85°C
0°C to 70°C
0°C to 70°C
-40°C to +85°C
0°C to 70°C
-40°C to +85°C
0°C to 70°C
-40°C to +85°C
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DS87C530/DS83C530
DS87C530/DS83C530 BLOCK DIAGRAM
Figure 1
PIN DESCRIPTION
Table 1
PLCC
52
1, 25
29
26
12
TQFP
45
18, 46
22
19
5
SIGNAL
NAME
V
CC
GND
V
CC2
GND2
RST
DESCRIPTION
V
CC
- +5V.
Processor power supply.
GND
- Processor digital circuit ground.
V
CC2
- +5V Real Time Clock supply. V
CC2
is isolated from V
CC
to
isolate the RTC from digital noise.
GND2
- Real Time Clock circuit ground.
RST - Input.
This pin contains a Schmitt voltage input to
recognize external active high Reset inputs. The pin also employs
an internal pulldown resistor to allow for a combination of wired
OR external Reset sources. An RC is not required for power-up, as
the device provides this function internally.
XTAL1, XTAL2
- The crystal oscillator pins provide support for
parallel resonant, AT cut crystals. XTAL1 acts also as an input if
there is an external clock source in place of a crystal. XTAL2 is
the output of the crystal amplifier.
23
24
16
17
XTAL2
XTAL1
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DS87C530/DS83C530
PLCC
38
TQFP
31
SIGNAL
NAME
PSEN
PSEN
DESCRIPTION
- Output.
The Program Store Enable output. This signal is a
chip enable for optional external ROM memory.
PSEN
will
provide an active low pulse and is driven high when external
ROM is not being accessed.
ALE - Output.
The Address Latch Enable output latches the
external address LSB from the multiplexed address/data bus on
Port 0. This signal is commonly connected to the latch enable of
an external 373 family transparent latch. ALE has a pulse width of
1.5 XTAL1 cycles and a period of four XTAL1 cycles. ALE is
forced high when the device is in a Reset condition. ALE can be
disabled and forced high by writing ALEOFF=1 (PMR.2). ALE
operates independently of ALEOFF during external memory
accesses.
Port 0 (AD0-7) - I/O.
Port 0 is an open-drain, 8-bit bi-directional
I/O port. As an alternate function Port 0 can function as the
multiplexed address/data bus to access off-chip memory. During
the time when ALE is high, the LSB of a memory address is
presented. When ALE falls to a logic 0, the port transitions to a bi-
directional data bus. This bus is used to read external ROM and
read/ write external RAM memory or peripherals. When used as a
memory bus, the port provides active high drivers. The reset
condition of Port 0 is tri-state. Pullup resistors are required when
using Port 0 as an I/O port.
Port 1 - I/O.
Port 1 functions as both an 8-bit bi-directional I/O
port and an alternate functional interface for Timer 2 I/O, new
External Interrupts, and new Serial Port 1. The reset condition of
Port 1 is with all bits at a logic 1. In this state, a weak pullup holds
the port high. This condition also serves as an input mode, since
any external circuit that writes to the port will overcome the weak
pullup. When software writes a 0 to any port pin, the device will
activate a strong pulldown that remains on until either a 1 is
written or a reset occurs. Writing a 1 after the port has been at 0
will cause a strong transition driver to turn on, followed by a
weaker sustaining pullup. Once the momentary strong driver turns
off, the port again becomes the output high (and input) state. The
alternate modes of Port 1 are outlined as follows.
Port Alternate
Function
P1.0 T2
External I/O for Timer/Counter 2
P1.1 T2EX
Timer/Counter 2 Capture/Reload Trigger
P1.2 RXD1
Serial Port 1 Input
P1.3 TXD1
Serial Port 1 Output
P1.4 INT2
External Interrupt 2 (Positive Edge Detect)
P1.5
INT3
External Interrupt 3 (Negative Edge Detect)
P1.6 INT4
External Interrupt 4 (Positive Edge Detect)
P1.7
INT5
External Interrupt 5 (Negative Edge Detect)
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39
32
ALE
50
49
48
47
46
45
44
43
43
42
41
40
39
38
37
36
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
3-10
48-52,
1-3
P1.0 - P1.7
3
4
5
6
7
8
9
10
48
49
50
51
52
1
2
3
DS87C530/DS83C530
PLCC
30
31
32
33
34
35
36
37
TQFP
23
24
25
26
27
28
29
30
SIGNAL
NAME
P2.0 (AD8)
P2.1 (AD9)
P2.2 (AD10)
P2.3 (AD11)
P2.4 (AD12)
P2.5 (AD13)
P2.6 (AD14)
P2.7 (AD15)
DESCRIPTION
Port 2 (A8-15) - I/O.
Port 2 is a bi-directional I/O port. The reset
condition of Port 2 is logic high. In this state, a weak pullup holds
the port high. This condition also serves as an input mode, since
any external circuit that writes to the port will overcome the weak
pullup. When software writes a 0 to any port pin, the device will
activate a strong pulldown that remains on until either a 1 is
written or a reset occurs. Writing a 1 after the port has been at 0
will cause a strong transition driver to turn on, followed by a
weaker sustaining pullup. Once the momentary strong driver turns
off, the port again becomes both the output high and input state.
As an alternate function Port 2 can function as MSB of the
external address bus. This bus can be used to read external ROM
and read/write external RAM memory or peripherals.
Port 3 - I/O.
Port 3 functions as both an 8-bit bi-directional I/O
port and an alternate functional interface for external interrupts,
Serial Port 0, Timer 0 and 1 Inputs, and
RD
and
WR
strobes. The
reset condition of Port 3 is with all bits at a logic 1. In this state, a
weak pullup holds the port high. This condition also serves as an
input mode, since any external circuit that writes to the port will
overcome the weak pullup. When software writes a 0 to any port
pin, the device will activate a strong pulldown that remains on
until either a 1 is written or a reset occurs. Writing a 1 after the
port has been at 0 will cause a strong transition driver to turn on,
followed by a weaker sustaining pullup. Once the momentary
strong driver turns off, the port again becomes both the output
high and input state. The alternate modes of Port 3 are outlined
below.
Port Alternate
Function
P3.0 RXD0
Serial Port 0 Input
P3.1 TXD0
Serial Port 0 Output
External Interrupt 0
P3.2
INT0
P3.3
INT1
External Interrupt 1
P3.4 T0
Timer 0 External Input
P3.5 T1
Timer 1 External Input
P3.6
WR
External Data Memory Write Strobe
External Data Memory Read Strobe
P3.7
RD
EA
- Input.
Connect to ground to use an external ROM. Internal
RAM is still accessible as determined by register settings. Connect
to V
CC
to use internal ROM.
V
BAT
- Input.
Connect to the power source that maintains SRAM
and RTC when V
CC
< V
BAT
. May be connected to a 3V lithium
battery or a super-cap. Connect to GND if battery will not be used
with device.
15-22
8-15
P3.0 - P3.7
15
16
17
18
19
20
21
22
42
8
9
10
11
12
13
14
15
35
EA
51
44
V
BAT
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