DS78C120 DS88C120 Dual CMOS Compatible Differential Line Receiver
February 1996
DS78C120 DS88C120 Dual CMOS Compatible
Differential Line Receiver
General Description
The DS78C120 and DS88C120 are high performance dual
differential CMOS compatible line receivers for both bal-
anced and unbalanced digital data transmission The inputs
are compatible with EIA Federal and MIL standards
Input specifications meet or exceed those of the popular
DS7820 DS8820 line receiver
The line receiver will discriminate a
g
200 mV input signal
over a common-mode range of
g
10V and a
g
300 mV sig-
nal over a range of
g
15V
Circuit features include hysteresis and response control for
applications where controlled rise and fall times and or high
frequency noise rejection are desirable Threshold offset
control is provided for fail-safe detection should the input
be open or short Each receiver includes a 180X terminating
resistor and the output gate contains a logic strobe for time
discrimination The DS78C120 is specified over a
b
55 C to
a
125 C temperature range and the DS88C120 from 0 C to
a
70 C
Features
Y
Y
Y
Y
Y
Y
Y
Y
Y
Full compatibility with EIA Standards RS232-C RS422
and RS423 Federal Standards 1020 1030 and MIL-
188-114
Input voltage range of
g
15V (differential or common-
mode)
Separate strobe input for each receiver
1 2 V
CC
strobe threshold for CMOS compatibility
5k typical input impedance
50 mV input hysteresis
200 mV input threshold
Operation voltage range
e
4 5V to 15V
Separate fail-safe mode
Connection Diagram
Dual-In-Line Package
TL F 5801 – 1
Top View
Order Number DS88C120N
See NS Package Number N16A
For Complete Military 883 Specifications
see RETS Data Sheet
Order Number DS78C120J 883
See NS Package Number J16A
TRI-STATE is a registered trademark of National Semiconductor Corporation
C
1996 National Semiconductor Corporation
TL F 5801
RRD-B30M36 Printed in U S A
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www national com
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
18V
Input Voltage
Strobe Voltage
Output Sink Current
Maximum Power Dissipation at 25 C
Cavity Package
Molded Package
g
25V
Absolute Maximum Ratings
Storage Temperature Range
b
65 C to
a
150 C
Lead Temperature (Soldering 4 seconds)
260 C
Operating Conditions
Supply Voltage (V
CC
)
Temperature (T
A
)
DS78C120
DS88C120
Common-Mode Voltage (V
CM
)
Min
45
b
55
18V
50 mA
1433 mW
1362 mW
Max
15
a
125
a
70
a
15
Units
V
C
C
V
0
b
15
Derate cavity package 9 6 mW C above 25 C derate molded package
10 9 mW C above 25 C
Electrical Characteristics
(Notes 2 and 3)
Symbol
V
TH
Parameter
Differential Threshold
Voltage
Differential Threshold
Voltage
Differential Threshold
Voltage Fail-Safe
Offset
e
5V
Input Resistance
I
OUT
e b
200
mA
V
OUT
t
V
CC
b
1 2V
I
OUT
e
1 6 mA V
OUT
s
0 5V
Conditions
b
7V
s
V
CM
s
7V
b
15V
s
V
CM
s
15V
b
7V
s
V
CM
s
7V
b
15V
s
V
CM
s
15V
Min
Typ
0 06
0 06
b
0 08
b
0 08
Max Units
02
03
b
0 2
b
0 3
V
V
V
V
V
V
kX
V
TL
V
TH
V
TL
R
IN
R
T
R
O
I
IND
I
OUT
e b
200
mA
V
OUT
t
V
CC
b
1 2V
I
OUT
e
1 6 mA V
OUT
s
0 5V
b
7V
s
V
CM
s
7V
b
7V
s
V
CM
s
7V
0 47
02
4
100
0 42
5
180
56
07
b
15V
s
V
CM
s
15V 0V
s
V
CC
s
15V
Line Termination Resistance T
A
e
25 C
Offset Control Resistance
Data Input Current
(Unterminated)
T
A
e
25 C
0V
s
V
CC
s
15V
V
CM
e
10V
V
CM
e
0V
V
CM
e b
10V
300
X
kX
2
0
b
2
31
b
0 5
b
3 1
mA
mA
mA
V
V
V
V
THB
Input Balance
(Note 5)
I
OUT
e
200
mA
V
OUT
t
V
CC
b
1 2V R
S
e
500X
I
OUT
e
1 6 mA V
OUT
s
0 5V
R
S
e
500X
b
7V
s
V
CM
s
7V
b
7V
s
V
CM
s
7V
01
b
0 1
04
b
0 4
V
OH
V
OL
I
CC
Logical ‘‘1’’ Output Voltage
Logical ‘‘0’’ Output Voltage
Power Supply Current
I
OUT
e b
200
mA
V
DIFF
e
1V
I
OUT
e
1 6 mA V
DIFF
e b
1V
15V
s
V
CM
s
b
15V
V
DIFF
e b
0 5V (Both Receivers)
V
STROBE
e
15V V
DIFF
e
3V
V
STROBE
e
0V V
DIFF
e b
3V
V
OL
s
0 5V I
OUT
e
1 6 mA
V
CC
e
5V
V
CC
e
10V
V
CC
e
15V
V
CC
e
5 5V
V
CC
e
15V
V
CC
b
1 2 V
CC
b
0 75
0 25
8
15
15
b
0 5
05
15
30
100
b
100
V
mA
mA
mA
mA
V
V
V
I
IN(1)
I
IN(0)
V
IH
Logical ‘‘1’’ Strobe Input
Current
Logical ‘‘0’’ Strobe Input
Current
Logical ‘‘1’’ Strobe Input
Voltage
35
80
12 5
25
50
75
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Electrical Characteristics
(Notes 2 and 3) (Continued)
Symbol
V
IL
Parameter
Logical ‘‘0’’ Strobe Input
Voltage
V
OH
V
CC
b
1 2V
I
OUT
e b
200
mA
Conditions
V
CC
e
5V
V
CC
e
10V
V
CC
e
15V
I
OS
Output Short-Circuit Current
V
OUT
e
0V V
CC
e
15V V
STROBE
e
0V (Note 4)
b
5
Min
Typ
25
50
75
b
20
Max
15
20
25
b
40
Units
V
V
V
mA
Note 1
‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation
Note 2
Unless otherwise specified min max limits apply across the
b
55 C to
a
125 C temperature range for the DS78C120 and across the 0 C to
a
70 C range
for the DS88C120 All typical values for T
A
e
25 C V
CC
e
5V and V
CM
e
0V
Note 3
All currents into device pins shown as positive out of device pins as negative all voltages referenced to ground unless otherwise noted All values shown
as max or min on absolute value basis
Note 4
Only one output at a time should be shorted
Note 5
Refer to EIA-RS422 for exact conditions
Switching Characteristics
V
CC
e
5V
Symbol
t
pd0(D)
t
pd1(D)
t
pd0(S)
t
pd1(S)
Parameter
Differential Input to ‘‘0’’ Output
Differential Input to ‘‘1’’ Output
Strobe Input to ‘‘0’’ Output
Strobe Input to ‘‘1’’ Output
T
A
e
25 C
Conditions
C
L
e
50 pF
C
L
e
50 pF
C
L
e
50 pF
C
L
e
50 pF
Min
Typ
60
100
30
100
Max
100
150
70
150
Units
ns
ns
ns
ns
AC Test Circuit and Switching Time Waveforms
Differential and Strobe Input Signal
Includes probe and test fixture capacitance
TL F 5801 – 3
t
r
e
t
f
s
10 ns
PRR
e
1 MHz
Note
Optimum switching response is obtained by minimizing stray capacitance on Response Control pin (no external connection)
TL F 5801 – 4
3
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4
TL F 5801 – 2
Schematic Diagram
(
Circuit Shown)
Application Hints
Balanced Data Transmission
TL F 5801 – 5
Unbalanced Data Transmission
TL F 5801 – 6
Logic Level Translator
TL F 5801 – 8
TL F 5801 –7
The DS78C120 DS88C120 may be used as a level transistor to interface between
g
12V MOS ECL TTL and CMOS To configure bias either input to a voltage
equal to
the voltage of the input signal and the other input to the driving gate
