If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
CMOS/TTL Input Voltage
LVDS Driver Output Voltage
LVDS Output Short Circuit
Duration
Junction Temperature
Storage Temperature
Lead Temperature
(Soldering, 4 sec)
MTD56 (TSSOP) Package:
DS90CF383B
−0.3V to +4V
−0.3V to (V
CC
+ 0.3V)
−0.3V to (V
CC
+ 0.3V)
Continuous
+150˚C
−65˚C to +150˚C
+260˚C
Package Derating:
DS90CF383B
ESD Rating
(HBM, 1.5 kΩ, 100 pF)
(EIAJ, 0Ω, 200 pF)
12.5 mW/˚C above +25˚C
7 kV
500V
Recommended Operating
Conditions
Min
Supply Voltage (V
CC
)
Operating Free Air
Temperature (T
A
)
Supply Noise Voltage (V
CC
)
TxCLKIN frequency
18
−10
+25
+70
200
68
˚C
mV
PP
MHz
3.0
Nom
3.3
Max
3.6
Units
V
Maximum Package Power Dissipation Capacity
@
25˚C
1.63 W
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
V
IH
V
IL
V
CL
I
IN
Parameter
High Level Input Voltage
Low Level Input Voltage
Input Clamp Voltage
Input Current
I
CL
= −18 mA
V
V
LVDS DC SPECIFICATIONS
V
OD
∆V
OD
V
OS
∆V
OS
I
OS
I
OZ
Differential Output Voltage
Change in V
OD
between
complimentary output states
Offset Voltage (Note 4)
Change in V
OS
between
complimentary output states
Output Short Circuit Current
Output
TRI-STATE
®
Current
V
OUT
= 0V, R
L
= 100Ω
Power Down = 0V,
V
OUT
= 0V or V
CC
R
L
= 100Ω,
C
L
= 5 pF,
Worst Case Pattern
(Figures 1, 4 )
" Typ "
values are given for V
CC
= 3.6V and T
A
=
+25˚C, " Max " values
are given for V
CC
=
3.6V and T
A
= −10˚C
f = 25 MHz
−3.5
1.13
1.25
R
L
= 100Ω
250
345
450
35
1.38
35
−5
mV
mV
V
mV
mA
µA
IN
IN
Conditions
Min
2.0
GND
Typ
Max
V
CC
0.8
Units
V
V
V
µA
µA
CMOS/TTL DC SPECIFICATIONS
−0.79
+1.8
−10
0
−1.5
+10
= 0.4V, 2.5V or V
CC
= GND
±
1
±
10
TRANSMITTER SUPPLY CURRENT
ICCTW
Transmitter Supply Current
Worst Case
31
45
mA
f = 40 MHz
37
50
mA
f = 65 MHz
48
60
mA
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2
DS90CF383B
Electrical Characteristics
Symbol
ICCTG
Parameter
Transmitter Supply Current
16 Grayscale
TRANSMITTER SUPPLY CURRENT
(Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Conditions
R
L
= 100Ω,
C
L
= 5 pF,
16 Grayscale Pattern
(Figures 2, 4 )
" Typ "
values are given for V
CC
= 3.6V and T
A
=
+25˚C, " Max " values
are given for V
CC
=
3.6V and T
A
= −10˚C
f = 25 MHz
Min
Typ
29
Max
40
Units
mA
f = 40 MHz
33
45
mA
f = 65 MHz
39
50
mA
ICCTZ
Transmitter Supply Current
Power Down
Power Down = Low
Driver Outputs in TRI-STATE under
Power Down Mode
17
150
µA
Note 1:
“Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2:
Typical values are given for V
CC
= 3.3V and T
A
= +25˚C unless specified otherwise.
Note 3:
Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except V
OD
and
∆V
OD
).
Note 4:
V
OS
previously referred as V
CM
.
Recommended Transmitter Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
TCIT
TCIP
TCIH
TCIL
TXIT
TXPD
TxCLK IN Period
(Figure 6 )
TxCLK IN High Time
(Figure 6 )
TxCLK IN Low Time
(Figure 6)
TxIN, and Power Down pin Transition Time
Minimum pulse width for Power Down pin signal
Parameter
TxCLK IN Transition Time
(Figure 5 )
14.7
0.35T
0.35T
1.5
1
T
0.5T
0.5T
Min
Typ
Max
5
50
0.65T
0.65T
6
Units
ns
ns
ns
ns
ns
us
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
LLHT
LHLT
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
Parameter
LVDS Low-to-High Transition Time
(Figure 4 )
LVDS High-to-Low Transition Time
(Figure 4 )
Transmitter Output Pulse Position for Bit 0
(Figure 11 )
(Note 5)
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
Transmitter Output Pulse Position for Bit 0
(Figure 11 )
(Note 5)
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
f = 40
MHz
f = 65
MHz
−0.20
2.00
4.20
6.39
8.59
10.70
12.99
−0.25
3.32
6.89
10.46
14.04
17.61
21.18
Min
Typ
0.75
0.75
0
2.20
4.40
6.59
8.79
10.99
13.19
0
3.57
7.14
10.71
14.29
17.86
21.43
Max
1.4
1.4
+0.20
2.40
4.60
6.79
8.99
11.19
13.39
+0.25
3.82
7.39
10.96
14.54
18.11
21.68
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
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DS90CF383B
Transmitter Switching Characteristics
Symbol
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TSTC
THTC
TCCD
Parameter
(Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Min
f = 25
MHz
−0.450
5.26
10.98
16.69
22.41
28.12
33.84
2.5
0.5
3.011
6.062
Typ
0
5.71
11.43
17.14
22.86
28.57
34.29
Max
+0.450
6.16
11.83
17.54
23.26
28.97
34.69
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Transmitter Output Pulse Position for Bit 0
(Figure 11 )
(Note 5)
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
TxIN Setup to TxCLK IN
(Figure 6 )
TxIN Hold to TxCLK IN
(Figure 6 )
TxCLK IN to TxCLK OUT Delay
(Figure 7 )
50% duty cycle input
clock is assumed, T
A
= −10˚C, and 65MHz for " Min ", T
A
= 70˚C,
and 25MHz for " Max ", V
CC
= 3.6V
Spread Spectrum Clock support; Modulation frequency with a linear
profile (Note 6)
f = 25
MHz
f = 40
MHz
f = 65
MHz
SSCG
100KHz
±
2.5%/−5%
100KHz
±
2.5%/−5%
100KHz
±
2.5%/−5%
10
100
ms
ns
TPLLS
TPDD
Transmitter Phase Lock Loop Set
(Figure 8 )
Transmitter Power Down Delay
(Figure 10 )
Note 5:
The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temperature ranges. This
parameter is functionality tested only on Automatic Test Equipment (ATE).
Note 6:
Care must be taken to ensure TSTC and THTC are met so input data are sampling correctly. This SSCG parameter only shows the performance of tracking
Spread Spectrum Clock applied to TxCLK IN pin, and reflects the result on TxCLKOUT+ and TxCLK− pins.
AC Timing Diagrams
20098504
FIGURE 1. “Worst Case” Test Pattern
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4
DS90CF383B
AC Timing Diagrams
(Continued)
20098505
FIGURE 2. “16 Grayscale” Test Pattern
(Notes 7, 8, 9, 10)
Note 7:
The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
Note 8:
The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed
to produce groups of 16 vertical stripes across the display.
Note 9:
Figures 1, 2
show a falling edge data strobe (TxCLK IN/RxCLK OUT).
Note 10:
Recommended pin to signal mapping. Customer may choose to define differently.
